DS3906U+T&R Maxim Integrated Products, DS3906U+T&R Datasheet - Page 11

• Manufacturer Part Number: DS3906U+T&R
• Description: IC RESIST VAR TRPL 10USOP
• Manufacturer: Maxim Integrated Products

Specifications of DS3906U+T&R

• Taps: 64
• Resistance (ohms): 1.45K, 2.54K, 2.54K
• Number Of Circuits: 3
• Temperature Coefficient: 60 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 1.45K, 2.54K, 2.54K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Repeated Start Condition: The master can use a
repeated start condition at the end of one data transfer to
indicate that it will immediately initiate a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start con-
dition, See the timing diagram for applicable timing.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 2). Data is
shifted into the device during the rising edge of the SCL.
Bit Read: At the end a write operation, the master must
release the SDA bus line for the proper amount of setup
time (see Figure 2) before the next rising edge of SCL
during a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. Remember that the master generates all
SCL clock pulses including when it is reading bits from
the slave.
Acknowledgement
Acknowledgement (ACK) or Not Acknowledge (NACK)
is always the 9
The device receiving data (the master during a read or
the slave during a write operation) performs an ACK by
transmitting a zero during the 9th bit. A device per-
forms a NACK by transmitting a one during the 9th bit.
Timing (Figure 2) for the ACK and NACK is identical to
all other bit writes. An ACK is the acknowledgment that
the device is properly receiving data. A NACK is used
to terminate a read sequence or as an indication that
the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgement from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgement is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minated communication so the slave will return control
of SDA to the master.
th
bit transmitted during a byte transfer.
(ACK
and
Triple NV Low Step Size Variable
____________________________________________________________________
NACK):
An
Slave Address Byte: Each slave on the I
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7-bits
and the
The DS3906’s slave address is determined by the state
of the A0, A1, and A2 address pins as shown in Figure
1. Address pins tied to GND result in a ‘0’ in the corre-
sponding bit position in the slave address. Conversely,
address pins tied to V
sponding bit positions.
When the R/W bit is 0 (such as in A0h), the master is
indicating it writes data to the slave. If R/W = 1, (A1h in
this case), the master is indicating it wants to read from
the slave.
If an incorrect slave address is written, the DS3906
assumes the master is communicating with another I
device and ignore the communication until the next
start condition is sent.
Memory Address: During an I
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
Writing a Single Byte to a Slave: The master must
generate a start condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data and generate a stop condition. Remember the
master must read the slave’s acknowledgement during
all byte write operations.
Writing Multiple Bytes to a Slave: The DS3906 is
capable of writing up to 2 bytes (1-page or row) in a
single write transaction. This is internally controlled by
an address counter that allows data to be written to
consecutive addresses without transmitting a memory
address before each data byte is sent. The address
counter limits the write to one 2-byte page. Pages
begin on even addresses (00h, 02h, 04h, etc).
Attempts to write more than 2 bytes of memory without
at once without sending a stop condition between
pages results in the address counter wrapping around
to the beginning of the present row.
To write multiple bytes to a slave in one transaction, the
master generates a start condition, writes the slave
address byte (R/W =0), writes the memory address (must
be even), writes two data bytes, and generates a stop
condition. Remember the master must read the slave’s
acknowledgement during all byte write operations.
Resistor Plus Memory
R/W bit in the least significant bit.
CC
result in a ‘1’ in the corre-
I
2
2
C Communication
C write operation, the
2
C bus
2
11
C