PIC18F66K22-I/PT Microchip Technology, PIC18F66K22-I/PT Datasheet - Page 436
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F66K22-I/PT
Manufacturer Part Number
PIC18F66K22-I/PT
Description
64kB Flash, 4kB RAM, 1kB EE, NanoWatt XLP, GP 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F66K22-IPT.pdf
(548 pages)
2.PIC18F66K22-IPT.pdf
(548 pages)
3.PIC18F66K22-IPT.pdf
(8 pages)
Specifications of PIC18F66K22-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F66K22-I/PT
Manufacturer:
EPCOS
Quantity:
3 000
Company:
Part Number:
PIC18F66K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F66K22-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F66K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K22 FAMILY
ADDWFC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39960B-page 436
Q Cycle Activity:
Before Instruction
After Instruction
Decode
Carry bit =
REG
W
Carry bit =
REG
W
Q1
=
=
=
=
register ‘f’
ADD W and Carry bit to f
ADDWFC
0 f 255
d [0,1]
a [0,1]
(W) + (f) + (C) dest
N,OV, C, DC, Z
Add W, the Carry flag and data memory
location ‘f’. If ‘d’ is ‘ 0 ’, the result is
placed in W. If ‘d’ is ‘ 1 ’, the result is
placed in data memory location ‘f’.
If ‘a’ is ‘ 0 ’, the Access Bank is selected.
If ‘a’ is ‘ 1 ’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘ 0 ’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
ADDWFC
Read
0010
Q2
1
02h
4Dh
0
02h
50h
00da
REG, 0, 1
f {,d {,a}}
Process
Data
Q3
ffff
destination
Write to
Q4
ffff
Preliminary
ANDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
W
Q1
Read literal
=
=
AND Literal with W
ANDLW
0 k 255
(W) .AND. k W
N, Z
The contents of W are ANDed with the
8-bit literal ‘k’. The result is placed in W.
1
1
ANDLW
0000
Q2
‘k’
A3h
03h
2010 Microchip Technology Inc.
k
1011
05Fh
Process
Data
Q3
kkkk
Write to
Q4
W
kkkk
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