TWR-AUDIO-SGTL Freescale Semiconductor, TWR-AUDIO-SGTL Datasheet - Page 13

• Manufacturer Part Number: TWR-AUDIO-SGTL
• Description: TWR SYS Audio Board
• Manufacturer: Freescale Semiconductor
• Series: Kinetisr

Specifications of TWR-AUDIO-SGTL

• Kit Contents: TWR-AUDIO-SGTL Featuring SGTL5000 Low Power Stereo Codec, Printed Quick Start Guide
• Mcu Supported Families: K20, K50, MCF51Jx
• Kit Features: SGTL5000 Low Power Stereo Codec With Headphone
• Rohs Compliant: Yes
• Design Resources: TWR-AUDIO-SGTL Schematics
• Accessory Type: Module, Audio with CODEC
• Description/function: Audio CODECs
• Mounting Style: Press Fit
• Product: Audio Modules
• Features: SGTL5000 Low Power Stereo Codec With Headphone Amplifier, Stereo Line-in / Line-out On 3.5mm Jack
• Lead Free Status / Rohs Status: Details
• For Use With/related Products: Freescale Tower System

Table 6. Synchronous MCLK Rates
Using the PLL - Asynchronous SYS_MCLK input
any clock from 8.0 to 27 MHz to be connected to SYS_MCLK.
This can help save system costs, as a clock available
elsewhere in the system can be used to derive all audio
clocks using the internal PLL. In this case, the clock input to
SYS_MCLK can be asynchronous with the sampling
frequency needed in the system. For example, a 12 MHz
MCLK, for a 48 kHz frame clock
SYS_MCLK < 17 MHz
(196.608 MHz/12 MHz) = 16 (decimal)
12 MHz) - 16) * 2048 = 786 (decimal)
Analog Integrated Circuit Device Data
Freescale Semiconductor
Notes
System Master Clock (SYS_MCLK)
Sampling Frequency (Fs)
An integrated PLL is provided in the SGTL5000 that allows
For example, when a 12 MHz digital signal is placed on
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0 //
CHIP_PLL_CTRL->INT_DIVISOR = FLOOR
CHIP_PLL_CTRL->FRAC_DIVISOR = ((196.608 MHz/
Refer to PLL programming
6.
For a sampling frequency of 96 kHz, only 256 Fs SYS_MCLK is supported
CHIP_CLK_TOP _CTRL->INPUT_FREQ_DIV2 = 1
PLL_INPUT_FREQ = SYS_MCLK/2
CHIP_PLL_CTRL->INT_DIVISOR = FLOOR (PLL_OUTPUT_FREQ/INPUT_FREQ
CHIP_PLL_CTRL->FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) - INT_DIVISOR) * 2048
CLOCK
PLL_OUTPUT_FREQ=180 .6336 MHz
PLL
Configuration.
Figure 9. PLL Programming Flowchart
Yes
Yes
SYS_MCLK>17MHz?
256, 384, 512
8, 11.025, 16, 22.5, 32, 44.1, 48, 96
Frequency =
44.1kHz?
Sampling
clock from the system processor could be used as the clock
input to the SGTL5000.
the PLL. They are CHIP_PLL_CTRL->INT_DIVISOR,
CHIP_PLL_CTRL->FRAC_DIVISOR and
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2.
shows a flowchart that shows how to determine the values to
program in the register fields.
the signal flow from input to output. Any single input can be
routed to any single or multiple outputs.
(DAP). The output of the DAP (an input to the audio switch)
can in turn be routed to any physical output. The output of the
DAP can not be routed into itself. Refer to
Processing, for DAP information and configuration.
to headphone output does not go through the audio switch.
AUDIO SWITCH (SOURCE SELECT SWITCH)
PLL_OUTPUT_FREQ=196 .608 MHz
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0
PLL_INPUT_FREQ = SYS_MCLK
Three register fields need to be configured to properly use
The audio switch is the central routing block that controls
Any signal can be routed to the Digital Audio Processor
It should be noted that the analog bypass from Line input
SUPPORTED RATES
No
No
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
(6)
FUNCTIONAL DESCRIPTION
Fs
kHz
Digital Audio
UNITS
Figure 9
SGTL5000
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