DS1847B-010+T&R Maxim Integrated Products, DS1847B-010+T&R Datasheet - Page 5
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DS1847B-010+T&R
Manufacturer Part Number
DS1847B-010+T&R
Description
IC RES TEMP-CNTRL 10/10K 16-BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1847E-050.pdf
(17 pages)
Specifications of DS1847B-010+T&R
Taps
256
Resistance (ohms)
10K
Number Of Circuits
2
Temperature Coefficient
850 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 95°C
Mounting Type
Surface Mount
Package / Case
16-CSBGA
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Memory
Location
E2h
E3h
E4h
E5h to E6h
E7h
E8h to EFh
F0h
F1h
F2h to FFh
User Memory
User Memory
User memory
Name of Location
Temperature MSB
Temperature LSB
Address Pointer
Address Select
Resistor 0 Setting
Resistor 1 Setting
5 of 17
Function of Location
This byte contains the MSB of the 13-bit 2s
complement temperature output from the
temperature sensor.
complement temperature output from the
temperature sensor.
For example temperature readings, refer to Table
2.
Calculated, current resistor address (0h – 47h).
The user-defined resistor setting at this location in
the respective look-up table will be loaded into
F0h and F1h to set the two resistors.
General purpose user memory (SRAM)
Internal or external device address select. This
byte allows the user to use the external address
pins or an internal register location to determine
the device address.
ENB = 0 and external A2, A1, A0 grounded,
device will use internal address bits (A2, A1, A0)
in this register
ENB = 1, external A2, A1, A0 = any setting,
device will use external address pins
Default setting is 01h. The device uses external
pins to determine its address.
General purpose user memory (SRAM)
In the user-controlled setting mode, this block
contains the resistor 0 setting.
In the user-controlled setting mode, this block
contains the resistor 1 setting.
General purpose user memory (SRAM)
This byte contains the LSB of the 13-bit 2s
2
S 2
0
2
-1
7
2
2
6
-2
2
2
5
-3
A2 A1 A0 ENB
2
2
4
-4
2
X X X
3
2
2
2
1