DS1858E-050 Maxim Integrated Products, DS1858E-050 Datasheet - Page 19

• Manufacturer Part Number: DS1858E-050
• Description: IC RES TEMP 50/50K 3MON 16-TSSOP
• Manufacturer: Maxim Integrated Products

Specifications of DS1858E-050

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 2
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 95°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

section). If the address does not match, this part
returns to a low-power mode.
After receiving a matching address byte with the R/W
bit set low, provided there is no write protect, the
device goes into the write mode of operation (see the
Memory Organization section). The master must trans-
mit an 8-bit EEPROM memory address to the device to
define the address where the data is to be written. After
the byte has been received, the DS1858 transmits a
zero for one clock cycle to acknowledge the address
has been received. The master must then transmit an
8-bit data word to be written into this address. The
DS1858 again transmits a zero for one clock cycle to
acknowledge the receipt of the data. At this point, the
master must terminate the write operation with a stop
condition. The DS1858 then enters an internally timed
write process t
disabled during this byte write cycle.
The DS1858 is capable of an 8-byte page write. A page
is any 8-byte block of memory starting with an address
evenly divisible by eight and ending with the starting
address plus seven. For example, addresses 00h
through 07h constitute one page. Other pages would
be addresses 08h through 0Fh, 10h through 17h, 18h
through 1Fh, etc.
A page write is initiated the same way as a byte write,
but the master does not send a STOP condition after
the first byte. Instead, after the slave acknowledges the
data byte has been received, the master can send up
to seven more bytes using the same nine-clock
sequence. The master must terminate the write cycle
with a STOP condition or the data clocked into the
DS1858 will not be latched into permanent memory.
The address counter rolls on a page during a write. The
counter does not count through the entire address
space as during a read. For example, if the starting
address is 06h and 4 bytes are written, the first byte
goes into address 06h. The second goes into address
07h. The third goes into address 00h (not 08h). The
fourth goes into address 01h. If more than 9 bytes or
more are written before a STOP condition is sent, the
first bytes sent are overwritten. Only the last 8 bytes of
data are written to the page.
Acknowledge Polling: Once the internally timed write
has started and the DS1858 inputs are disabled,
acknowledge polling can be initiated. The process
involves transmitting a start condition followed by the
device address. The R/W bit signifies the type of opera-
tion that is desired. The read or write sequence will only
w
to the EEPROM memory. All inputs are
Write Operations
____________________________________________________________________
Resistors with Three Monitors
Page Write
Dual Temperature-Controlled
be allowed to proceed if the internal write cycle has
completed and the DS1858 responds with a zero.
After receiving a matching address byte with the R/W bit
set high, the device goes into the read mode of opera-
tion. There are three read operations: current address
read, random read, and sequential address read.
The DS1858 has an internal address register that main-
tains the address used during the last read or write
operation, incremented by one. This data is maintained
as long as V
the last byte in memory, then the register resets to the
first address.
Once the device address is clocked in and acknowl-
edged by the DS1858 with the R/W bit set to high, the
current address data word is clocked out. The master
does not respond with a zero, but does generate a stop
condition afterwards.
A random read requires a dummy byte write sequence to
load in the data byte address. Once the device and data
address bytes are clocked in by the master, and
acknowledged by the DS1858, the master must generate
another start condition. The master now initiates a current
address read by sending the device address with the
R/W bit set high. The DS1858 acknowledges the device
address and serially clocks out the data byte.
Sequential reads are initiated by either a current
address read or a random address read. After the mas-
ter receives the first data byte, the master responds
with an acknowledge. As long as the DS1858 receives
this acknowledge after a byte is read, the master can
clock out additional data words from the DS1858. After
reaching address FFh, it resets to address 00h.
The sequential read operation is terminated when the
master initiates a stop condition. The master does not
respond with a zero.
For a more detailed description of 2-wire theory of
operation, see the following section.
The 2-wire serial port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a trans-
mitter, and a device receiving data as a receiver. The
device that controls the message is called a master.
The devices that are controlled by the master are
2-Wire Serial Port Operation
CC
is valid. If the most recent address was
Sequential Address Read
Current Address Read
Read Operations
Single Read
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