CAT5401YI-10-T2 ON Semiconductor, CAT5401YI-10-T2 Datasheet - Page 4

• Manufacturer Part Number: CAT5401YI-10-T2
• Description: IC POT DPP QUAD 64TAP SPI 24TSSO
• Manufacturer: ON Semiconductor

Specifications of CAT5401YI-10-T2

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.5 V ~ 6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
SI: Serial Input
opcodes, byte addresses and data to be written to the
CAT5401. Input data is latched on the rising edge of the
serial clock.
SO: Serial Output
data out of the CAT5401. During a read cycle, data is shifted
out on the falling edge of the serial clock.
SCK: Serial Clock
the communication between the microcontroller and the
CAT5401. Opcodes, byte addresses or data present on the SI
pin are latched on the rising edge of the SCK. Data on the SO
pin is updated on the falling edge of the SCK.
A0, A1: Device Address Inputs
multiple devices. A total of four devices can be addressed on
a single bus. A match in the slave address must be made with
the address input in order to initiate communication with the
CAT5401.
R
terminal connections on a mechanical potentiometer.
R
a mechanical potentiometer.
CS: Chip Select
and CS high disables the CAT5401. CS high takes the SO
output pin to high impedance and forces the devices into a
Standby mode (unless an internal write operation is
underway). The CAT5401 draws ZERO current in the
Standby mode. A high to low transition on CS is required
prior to any sequence being initiated. A low to high
transition on CS after a valid write sequence is what initiates
an internal write cycle.
WP: Write Protect
allow normal read/write operations when held high. When
WP is tied low, all non−volatile write operations to the Data
registers are inhibited (change of wiper control register is
allowed). WP going low while CS is still low will interrupt
a write to the registers. If the internal write cycle has already
been initiated, WP going low will have no effect on any write
operation.
H
W
SI is the serial data input pin. This pin is used to input all
SO is the serial data output pin. This pin is used to transfer
SCK is the serial clock pin. This pin is used to synchronize
These inputs set the device address when addressing
The four sets of R
The four R
CS is the Chip select pin. CS low enables the CAT5401
WP is the Write Protect pin. The Write Protect pin will
, R
: Wiper
L
: Resistor End Points
W
pins are equivalent to the wiper terminal of
H
and R
L
pins are equivalent to the
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4
HOLD: Hold
CAT5401 while in the middle of a serial sequence without
having to retransmit entire sequence at a later time. To pause,
HOLD must be brought low while SCK is low. The SO pin
is in a high impedance state during the time the part is
paused, and transitions on the SI pins will be ignored. To
resume communication, HOLD is brought high, while SCK
is low. (HOLD should be held high any time this function is
not being used.) HOLD may be tied high directly to V
tied to V
Serial Bus Protocol
protocol. The synchronous Serial Peripheral Interface (SPI)
helps the CAT5401 to interface directly with many of
today’s popular microcontrollers. The CAT5041 contains an
8−bit instruction register. The instruction set and the
operation codes are detailed in the instruction set Table 12.
byte will be received. The part is accessed via the SI pin, with
data being clocked in on the rising edge of SCK. The first
byte contains one of the six op−codes that define the
operation to be performed.
Device Operation
serial interface logic, four 6−bit wiper control registers and
sixteen 6−bit, non−volatile memory data registers. Each
resistor array contains 63 separate resistive elements
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (R
may be interchanged. The tap positions between and at the
ends of the series resistors are connected to the output wiper
terminals (R
point for each potentiometer is connected to its wiper
terminal at a time and is determined by the value of the wiper
control register. Data can be read or written to the wiper
control registers or the non−volatile memory data registers
via the SPI bus. Additional instructions allows data to be
transferred between the wiper control registers and each
respective potentiometer’s non−volatile data registers. Also,
the device can be instructed to operate in an “increment/
decrement” mode.
The HOLD pin is used to pause transmission to the
The CAT5041 supports the SPI bus data transmission
After the device is selected with CS going low the first
The CAT5401 is four resistor arrays integrated with SPI
CC
through a resistor.
W
) by a CMOS transistor switch. Only one tap
H
and R
L
). R
H
and R
L
are symmetrical and
CC
or