MCP4821-E/SN Microchip Technology, MCP4821-E/SN Datasheet - Page 21

• Manufacturer Part Number: MCP4821-E/SN
• Description: IC DAC 12BIT W/SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP4821-E/SN

• Number Of Converters: 1
• Package / Case: 8-SOIC (3.9mm Width)
• Settling Time: 4.5µs
• Number Of Bits: 12
• Data Interface: Serial, SPI™
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resolution: 12 bit
• Interface Type: Serial (3-Wire, SPI, Microwire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.0
5.1
The MCP4801/4811/4821 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, available on many microcontrollers, and
supports Mode 0,0 and Mode 1,1. Commands and data
are sent to the device via the SDI pin, with data being
clocked-in
communications are unidirectional and, thus, data
cannot be read out of the MCP4801/4811/4821
devices. The CS pin must be held low for the duration
of a write command. The write command consists of
16 bits and is used to configure the DAC’s control and
data latches.
input register that is used to configure and load the
DAC register for each device.
show the write command for each device.
Refer to
Table for detailed input and output timing specifications
for both Mode 0,0 and Mode 1,1 operation.
 2010 Microchip Technology Inc.
Figure 1-1
SERIAL INTERFACE
Overview
on
Register 5-1
the
and the SPI Timing Specifications
rising
to
Figure 5-1
edge
Register 5-3
of
to
SCK.
Figure 5-3
detail the
The
5.2
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin is then raised, causing the data to be
latched into the DAC’s input register.
The MCP4801/4811/4821 devices utilize a double-
buffered latch structure to allow the DAC output to be
synchronized with the LDAC pin, if desired.
By bringing down the LDAC pin to a low state, the
content stored in the DAC’s input register is transferred
into the DAC’s output register (V
updated.
All writes to the MCP4801/4811/4821 devices are
16-bit words. Any clocks after the first 16
ignored.
Configuration bits. The remaining 12 bits are data bits.
No data can be transferred into the device with CS
high. The data transfer will only occur if 16 clocks have
been transferred into the device. If the rising edge of
CS occurs prior, shifting of data into the input register
will be aborted.
MCP4801/4811/4821
Write Command
The
Most
Significant
OUT
DS22244B-page 21
four
), and V
th
clock will be
bits
OUT
are
is