CS4385-CQZ Cirrus Logic Inc, CS4385-CQZ Datasheet - Page 24

• Manufacturer Part Number: CS4385-CQZ
• Description: IC DAC 8CH 114DB 192KHZ 48LQFP
• Manufacturer: Cirrus Logic Inc

Specifications of CS4385-CQZ

• Package / Case: 48-LQFP
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 8
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 520mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Conversion Rate: 216 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 5 V
• Operating Temperature Range: + 85 C
• Maximum Power Dissipation: 390 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1154 - BOARD EVAL FOR CS4385 DAC
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1063

24
4.3.1
4.3.2
4.4
SDIN1
LRCK
SCLK
LRCK
SC LK
SD IN1
Oversampling Modes
The CS4365 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the M4, M3 and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-Speed
mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode
supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed Mode sup-
ports input sample rates up to 200 kHz and uses an oversampling ratio of 32x.
The auto-speed mode detect feature allows for the automatic selection of speed mode based off of the in-
coming sample rate. This allows the CS4365 to accept a wide range of sample rates with no external inter-
vention necessary. The auto-speed mode detect feature is available in both hardware and Software Mode.
OLM #1
OLM #1 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to
SCLK at 128 Fs. Six channels of MSB first 20-bit PCM data are input on SDIN1.
OLM #2
OLM #2 serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave to
SCLK at 256 Fs. Six channels of MSB first 24-bit PCM data are input on SDIN1.
SDINx
LRCK
SCLK
MSB
M SB
1 0
DAC _A1
DAC_A1
20 clks
24 clks
LSB
LS B
MSB
M SB
17 16
DAC_A2
DAC_A2
Left Channel
20 clks
Left C hannel
24 clks
15 14 13 12 11 10
Figure 13. Format 5 - Right-Justified 18-bit Data
64 clks
128 clks
LSB
LS B
Left Channel
Figure 14. Format 8 - One-Line Mode 1
Figure 15. Format 9 - One-Line Mode 2
32 clocks
MSB
M S B
DAC_A3
20 clks
DAC_A3
24 clks
9 8 7
LSB
LS B
6 5 4 3 2 1 0
MSB
M SB
DAC_B1
20 clks
DAC_B1
24 clks
LSB
LS B
17 16
MSB
M SB
15 14 13 12 11 10
Right Channel
DAC_B2
20 clks
DAC_B2
Right C hannel
24 clks
64 clks
128 clks
LSB
Right Channel
LS B
MSB
M SB
9 8 7
DAC_B3
20 clks
DAC_B3
24 clks
6 5 4 3 2 1 0
LSB
LS B
CS4365
DS670F2
MSB
M S B