AD5530BRUZ Analog Devices Inc, AD5530BRUZ Datasheet - Page 11

• Manufacturer Part Number: AD5530BRUZ
• Description: IC DAC 12BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5530BRUZ

• Data Interface: Serial
• Settling Time: 20µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 50kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: ± 10.8V To ± 13.2V, ± 13.5V To ± 16.5V
• Supply Current: 2mA
• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 50 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±1 LSB
• Maximum Settling Time: 20(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5530/AD5531 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5530/AD5531 requires a
16-bit data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in or asynchronously
under the control of LDAC.
The contents of the DAC register may be read using the readback
function. RBEN is used to frame the readback data, which is
clocked out on SDO. The following figures illustrate these DACs
interfacing with a simple 4-wire interface. The serial interface of
the AD5530/AD5531 may be operated from a minimum of
three wires.
AD5530/AD5531 to ADSP-21xx
An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 7. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control regis-
ter should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP. Alternatively,
the LDAC input could be tied permanently low and then the
update takes place automatically when TFS is taken high.
1 F
C1
8
SIGNAL
AD586
GND
ADDITIONAL PINS OMITTED FOR CLARITY
4
2
6
5
R1
10k
REFIN
REFAGND
AD5531
AD5530/
±
–15V
+15V
V
V
OUT
SS
DUTGND
V
GND
OUT
SIGNAL
GND
V
(–10V TO +10V)
OUT
AD5530/AD5531 to 8051 Interface
A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 8. TXD of the 8051 drives SCLK of the AD5530/
AD5531, while RXD drives the serial data line, SDIN. P3.3 and
P3.4 are bit-programmable pins on the serial port and are used
to drive SYNC and LDAC respectively.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user will have to ensure that the data in the
SBUF register is arranged correctly as the DAC expects MSB first.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.
The 8051 transmits data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC expects a
16-bit word, P3.3 must be left low after the first 8 bits are transferred.
After the second byte has been transferred, the P3.3 line is taken
high. The DAC may be updated using LDAC via P3.4 of the 8051.
AD5530/AD5531 to MC68HC11 Interface
Figure 9 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the DAC, while the MOSI
output drives the serial data lines, SDIN. SYNC is driven from
one of the port lines, in this case PC7.
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
ADDITIONAL PINS OMITTED FOR CLARITY
80C51/80L51
ADSP-2103
MC68HC11
ADSP-2101/
SCLK
MOSI
RXD
SCK
P3.4
P3.3
TXD
TFS
PC6
PC7
FO
DT
AD5530/AD5531
LDAC
SYNC
SDIN
SCLK
LDAC
SYNC
SDIN
SCLK
LDAC
SYNC
SDIN
SCLK
AD5531
AD5531
AD5531
AD5530/
AD5530/
AD5530/