AD5530BRUZ Analog Devices Inc, AD5530BRUZ Datasheet - Page 8

• Manufacturer Part Number: AD5530BRUZ
• Description: IC DAC 12BIT SRL IN/VOUT 16TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5530BRUZ

• Data Interface: Serial
• Settling Time: 20µs
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 60mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 50kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: ± 10.8V To ± 13.2V, ± 13.5V To ± 16.5V
• Supply Current: 2mA
• Package: 16TSSOP
• Resolution: 12 Bit
• Conversion Rate: 50 KSPS
• Architecture: R-2R
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Full Scale Error: ±2 LSB
• Integral Nonlinearity Error: ±1 LSB
• Maximum Settling Time: 20(Typ) us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5530/AD5531
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
REFAGND
REFIN
LDAC
SDIN
SYNC
RBEN
SCLK
SDO
CLR
PD
GND
NC
V
DUTGND
V
V
SS
OUT
DD
Level Sensitive, Active Low Input. A falling edge of CLR resets V
are untouched.
Description
For bipolar ±10 V output range, this pin should be tied to 0 V.
This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar ±10 V output.
Load DAC Logic Input (Active Low). When taken low, the contents of the shift register are transferred to the DAC
register. LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK.
Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK.
Active Low Readback Enable Function. This function allows the contents of the DAC register to be read. Data
from the DAC register is shifted out on the SDO pin on each rising edge of SCLK.
Clock Input. Data is clocked into the input register on the falling edge of SCLK.
Serial Data Out. This pin is used to clock out the serial data previously written to the input shift register or can be
used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output; it
should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left
high impedance.
This allows the DAC to be put into a power-down state.
Ground Reference.
Do not connect anything to this pin.
Negative Analog Supply Voltage. −12 V ± 10% or −15 V ± 10%, for specified performance.
V
DAC Output.
Positive Analog Supply Voltage. 12 V ± 10% or 15 V ± 10%, for specified performance.
OUT
is referenced to the voltage applied to this pin.
REFAGND
REFIN
SYNC
RBEN
LDAC
SCLK
SDIN
SDO
Figure 4. Pin Configuration
Rev. B | Page 8 of 20
1
2
3
4
5
6
7
8
NC = NO CONNECT
(Not to Scale)
AD5530/
AD5531
TOP VIEW
16
15
14
13
12
11
10
9
V
V
DUTGND
V
NC
GND
PD
CLR
DD
OUT
SS
OUT
to DUTGND. The contents of the registers