AD9762ARUZ Analog Devices Inc, AD9762ARUZ Datasheet - Page 5

• Manufacturer Part Number: AD9762ARUZ
• Description: IC DAC 12BIT 125MSPS 28-TSSOP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9762ARUZ

• Data Interface: Parallel
• Settling Time: 35ns
• Number Of Bits: 12
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 160mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AD9762-EB - BOARD EVAL FOR AD9762
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Pin No.
1
2–11
12
13, 14, 25 NC
15
16
17
18
19
20
21
22
23
24
26
27
28
REV. B
Name
DB11
DB10–DB1 Data Bits 1–10.
DB0
SLEEP
REFLO
REFIO
FS ADJ
COMP1
ACOM
IOUTB
IOUTA
COMP2
AVDD
DCOM
DVDD
CLOCK
Description
Most Significant Data Bit (MSB).
Least Significant Data Bit (LSB).
No Internal Connection.
Power-down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if
not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
Analog Supply Voltage (+2.7 V to +5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input. Data latched on positive edge of clock.
(MSB) DB11
PIN CONFIGURATION
PIN DESCRIPTIONS
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
NC
NC
10
11
12
13
14
8
9
1
2
3
4
5
6
7
NC = NO CONNECT
(Not to Scale)
TOP VIEW
AD9762
–5–
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
AD9762