MAX5512EUA+ Maxim Integrated Products, MAX5512EUA+ Datasheet - Page 5

• Manufacturer Part Number: MAX5512EUA+
• Description: IC DAC 8BIT DUAL VOUT 8-UMAX
• Manufacturer: Maxim Integrated Products

Specifications of MAX5512EUA+

• Settling Time: 660µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
• Number Of Dac Outputs: 2
• Resolution: 8 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 0.006 mA
• Voltage Reference: External
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
(V
TIMING CHARACTERISTICS
(V DD = +1.8V to +5.5V, T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A = +25°C.)
Note 1: Linearity is tested within codes 6 to 255.
Note 2: Offset is tested at code 6.
Note 3: Gain is tested at code 255. For the MAX5514/MAX5515, FB_ is connected to its respective OUT_.
Note 4: Guaranteed by design. Not production tested.
Note 5: V
Note 6: Outputs can be shorted to V
Note 7: Optimal noise performance is at 2nF load capacitance.
Note 8: Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T
Note 9: All digital inputs at V
Note 10: Load = 10kΩ in parallel with 100pF, V
TIMING CHARACTERISTICS (V
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Pulse-Width High
SCLK Rise to CS Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
TIMING CHARACTERISTICS (V
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Pulse-Width High
SCLK Rise to CS Rise Hold Time
CS Fall to SCLK Rise Setup Time
SCLK Fall to CS Fall Setup
CS Rise to SCK Rise Hold Time
DD
= +4.5V to +5.5V, T
DD
PARAMETER
PARAMETER
must be a minimum of 1.8V.
_______________________________________________________________________________________
A
= T
DD
MIN
or GND.
DD
DD
to T
= 4.5V to 5.5V )
= 1.8V to 5.5V )
DD
MAX
or GND indefinitely, provided that package power dissipation is not exceeded.
SYMBOL
SYMBOL
, unless otherwise noted. Typical values are at T
f
f
t
t
t
t
t
t
t
SCLK
t
SCLK
t
t
CSW
CSO
CSW
t
t
t
CSH
CSS
t
t
CSH
CSO
t
CS1
t
t
CSS
CS1
DS
DH
CH
DH
CH
CL
DS
CL
DD
= 5V, V REF = 4.096V (MAX5512/MAX5514) or V
8-Bit, Voltage-Output DACs
CONDITIONS
CONDITIONS
Dual, Ultra-Low-Power,
A
= +25°C.)
MIN
MIN
100
150
15
24
24
20
20
24
40
40
30
30
0
0
0
0
0
0
0
0
REF
= 3.9V (MAX5513/MAX5515).
TYP
TYP
MAX
MAX
16.7
10
MAX
to T
UNITS
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN
.
5