MAX530BCWG+ Maxim Integrated Products, MAX530BCWG+ Datasheet - Page 7

• Manufacturer Part Number: MAX530BCWG+
• Description: IC DAC PARA-IN V-OUT12BIT 24SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX530BCWG+

• Settling Time: 25µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Parallel
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 941 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 250 uA
• Voltage Reference: Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

* This applies to 4 + 4 + 4 input loading mode. See Table 2 for 8 + 4 input loading mode.
______________________________________________________________Pin Description
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
REFGND
REFOUT
D2/ D10
D3/ D11
NAME
DGND
AGND
D1/ D9
REFIN
D0/D8
LDAC
VOUT
ROFS
CLR
RFB
V
V
WR
CS
_______________________________________________________________________________________
D4
D5
D6
D7
A0
A1
DD
SS
D1 Input Dta, when A0 = 0 and A1 = 1, or D9 Input when A0 = A1 = 1*
D2 Input Dta, when A0 = 0 and A1 = 1, or D10 Input when A0 = A1 = 1*
D3 Input Dta, when A0 = 0 and A1 = 1, or D11 (MSB) Input when A0 = A1 =1*
D4 Input Dta, or tie to D0 and multiplex when A0 = 1 and A1 = 0*
D5 Input Dta, or tie to D1 and multiplex when A0 = 1 and A1 = 0*
D6 Input Dta, or tie to D2 and multiplex when A0 = 1 and A1 = 0*
D7 Input Dta, or tie to D3 and multiplex when A0 = 1 and A1 = 0*
Address Line A0. With A1, used to multiplex 4 of 12 data lines to load low (NBL), middle (NBM),
and high (NBH) 4-bit nibbles. (12 bits can also be loaded as 8+4.)
Address Line A1. Set A0 = A1 = 0 for NBL and NBM, A0 = 0 and A1 = 1 for NBL, A0 = 1 and
A1 = 0 for NBM, or A0 = A1 = 1 for NBH. See Table 2 for complete input latch addressing.
Write Input (active low). Used with CS to load data into the input latch selected by A0 and A1.
Chip Select (active low). Enables addressing and writing to this chip from common bus lines.
Digital Ground
Reference Input. Input for the R-2R DAC. Connect an external reference to this pin or a jumper to
REFOUT (pin 18) to use the internal 2.048V reference.
Analog Ground
Clear (active low). A low on CLR resets the DAC latches to all 0s.
Load DAC Input (active low). Driving this asynchronous input low transfers the contents of the input
latch to the DAC latch and updates VOUT.
Reference Ground must be connected to AGND when using the internal reference. Connect to V
to disable the internal reference and save power.
Reference Output. Output of the internal 2.048V reference. Tie to REFIN to drive the R-2R DAC.
Negative Power Supply. Usually ground for single-supply or -5V for dual-supply operation.
Voltage Output. Op-amp buffered DAC output.
Feedback Pin. Op-amp feedback resistor. Always connect to VOUT.
Offset Resistor Pin. Connect to VOUT for G = 1, to AGND for G = 2, or to REFIN for bipolar output.
Positive Power Supply (+5V)
D0 (LSB) Input Dta when A0 = 0 and A1 = 1, or D8 Input when A0 = A1= 1*
+5V, Low-Power, Parallel-Input,
Voltage-Output, 12-Bit DAC
FUNCTION
DD
7