MAX530BCAG+ Maxim Integrated Products, MAX530BCAG+ Datasheet - Page 11

• Manufacturer Part Number: MAX530BCAG+
• Description: IC DAC 12BIT PAR/VOLT I/O 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX530BCAG+

• Settling Time: 25µs
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Number Of Dac Outputs: 1
• Resolution: 12 bit
• Interface Type: Parallel
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 640 mW
• Minimum Operating Temperature: 0 C
• Supply Current: 250 uA
• Voltage Reference: Internal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 4. MAX530 Write-Cycle Timing Diagram
Designed to interface with 4-bit, 8-bit, and 16-bit micro-
processors (µPs), the MAX530 uses 8 data pins and
double-buffered logic inputs to load data as 4 + 4 + 4
or 8 + 4. The 12-bit DAC latch is updated simultane-
ously through the control signal LDAC. Signals A0, A1,
WR, and CS select which input latches to update. The
12-bit data is broken down into nibbles (NB); NBL is
the enable signal for the lowest 4 bits, NBM is the
enable for the middle 4 bits, and NBH is the enable for
the highest and most significant 4 bits. Table 2 lists the
address decoding scheme.
Refer to Figure 4 for the MAX530 write-cycle timing
diagram.
Figure 5 shows the circuit configuration for a 4-bit µP
application. Figure 6 shows the corresponding timing
sequence. The 4 low bits (D0-D3) are connected in paral-
lel to the other 4 bits (D4-D7) and then to the µP bus.
Address lines A0 and A1 enable the input data latches
(8-BIT BYTE OR
4-BIT NIBBLE)
DATA BITS
A0-A1
LDAC
CLR
WR
CS
NOTE: TIMING MEASUREMENT REFERENCE LEVEL IS
______________________________________________________________________________________
Parallel Logic Interface
t
CLR
+5V, Low-Power, Parallel-Input,
V
V
IH
IL
V
IH +
t
AWS
2
V
IL
Voltage-Output, 12-Bit DAC
ADDRESS BUS VALID
t
CWS
for the high, middle, or low data nibbles. The µP sends
chip select (CS) and write (WR) signals to latch in each of
three nibbles in three cycles when the data is valid.
Figure 7 shows a typical interface to an 8-bit or a 16-bit
µP. Connect 8 data bits from the data bus to pins D0-D7
on the MAX530. With LDAC held high, the user can load
NBH or NBL + NBM in any order. Figure 8a shows the
corresponding timing sequence. For fastest throughput,
use Figure 8b’s sequence. Address lines A0 and A1 are
tied together and the DAC is loaded in 2 cycles as 8 + 4.
In this scheme, with LDAC held low, the DAC latch is
transparent. Always load NBL and NBM first, followed by
NBH.
LDAC is asynchronous with respect to WR. If LDAC is
brought low before or at the same time WR goes high,
LDAC must remain low for at least 50ns to ensure the cor-
rect data is latched. Data is latched into DAC registers on
LDAC’s rising edge.
t
WR
V
V
IH
IL
t
DS
DATA BUS
VALID
t
AWH
t
DH
t
CWH
t
LDAC
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