MAX5873EGK+D Maxim Integrated Products, MAX5873EGK+D Datasheet - Page 9

• Manufacturer Part Number: MAX5873EGK+D
• Description: IC DAC 12BIT 200MSPS DUAL 68-QFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX5873EGK+D

• Settling Time: 14ns
• Number Of Bits: 12
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 300mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-QFN Exposed Pad
• Conversion Rate: 200 MSPs
• Resolution: 12 bit
• Interface Type: Parallel
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX5873 high-performance, 12-bit, dual current-
steering DAC (Figure 1) operates with DAC update rates
up to 200Msps. The converter consists of input registers
and a demultiplexer for single-port (interleaved) mode,
followed by a current-steering array. During operation in
interleaved mode, the input data registers demultiplex
the single-port data bus. The current-steering array gen-
erates differential full-scale currents in the 2mA to 20mA
range. An internal current-switching network, in combina-
tion with external 50Ω termination resistors, converts the
differential output currents into dual differential output
voltages with a 0.1V to 1V peak-to-peak output voltage
range. An integrated 1.2V bandgap reference, control
amplifier, and user-selectable external resistor determine
the data converter’s full-scale output range.
The MAX5873 supports operation with the internal 1.2V
bandgap reference or an external reference voltage
source. REFIO serves as the input for an external, low-
impedance reference source. REFIO also serves as a
reference output when the DAC operates in internal ref-
erence mode. For stable operation with the internal ref-
erence, decouple REFIO to GND with a 1µF capacitor.
Due to its limited output drive capability, buffer REFIO
with an external amplifier when driving large
external loads.
45–56
62–68
PIN
42
44
61
—
Reference Architecture and Operation
12-Bit, 200Msps, High-Dynamic-Performance,
A8, A7, A6, A5
A11, A10, A9
B11, B10, B9,
B8, B7, B6,
B5, B4, B3,
B2, B1, B0
DV
NAME
SELIQ
_______________________________________________________________________________________
XOR
EP
DD1.8
Detailed Description
DAC Exclusive-OR Select Input. Set XOR low to allow the data stream to pass unchanged to the
DAC input. Set XOR high to invert the input data into the DAC. If unused, connect XOR to GND.
DAC Select Input. Set SELIQ low to direct data into the Q-DAC inputs. Set SELIQ high to direct
data into the I-DAC inputs. If unused, connect SELIQ to GND. SELIQ’s logic state is only valid in
single-port (interleaved) mode.
Data Bits B11–B0. In dual-port mode, data is directed to the I-DAC. In single-port mode, the state
of SELIQ determines where the data bits are directed.
Digital Supply Voltage. Accepts a supply voltage range of 1.71V to 1.89V. Bypass with a 0.1µF
capacitor to GND.
Data Bits A11–A5. In dual-port mode, data is directed to the Q-DAC. In single-port mode, data bits
are not used. Connect bits A11–A5 to GND in single-port mode.
Exposed Pad. Must be connected to GND through a low-impedance path.
Architecture
Dual DAC with CMOS Inputs
The MAX5873’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
I
Configured as a voltage-to-current amplifier, calculate
the output current as follows:
where I
DAC. R
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I
and R
Table 1. I
Matrix Based on a Typical 1.200V
Reference Voltage
OUTFS
CURRENT I
SET
FULL-SCALE
FUNCTION
for the differential current outputs of the DAC.
OUTFS
SET
I
selections.
OUTFS
10
15
20
2
5
Pin Description (continued)
OUTFS
OUTFS
(located between FSADJ and DACREF)
is the full-scale output current of the
=
(mA)
32
and R
×
CALCULATED
V
R
REFIO
SET
SET
19.2k
7.68k
3.84k
2.56k
1.92k
Selection
×
R
SET
⎛
⎜
⎝
1
−
(Ω)
1% EIA STD
2
12
1
19.1k
3.83k
2.55k
1.91k
7.5k
⎞
⎟
⎠
OUTFS
9