MAX5853ETL+ Maxim Integrated Products, MAX5853ETL+ Datasheet - Page 17

IC DAC 10BIT 80MSPS DUAL 40-TQFN

MAX5853ETL+

Manufacturer Part Number
MAX5853ETL+
Description
IC DAC 10BIT 80MSPS DUAL 40-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX5853ETL+

Settling Time
12ns
Number Of Bits
10
Data Interface
Parallel
Number Of Converters
2
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
40-TQFN Exposed Pad
Number Of Dac Outputs
2
Resolution
10 bit
Interface Type
Parallel
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Maximum Power Dissipation
2105 mW
Minimum Operating Temperature
- 40 C
Supply Current
43.2 mA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Dissipation (max)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
The two-tone IMD is the ratio expressed in dBc of either out-
put tone to the worst 3rd-order (or higher) IMD products.
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. For a DAC,
the deviations are measured at every individual step.
Differential nonlinearity (DNL) is the difference between
an actual step height and the ideal value of 1 LSB. A
DNL error specification no more negative than -1 LSB
guarantees monotonic transfer function.
Offset error is the current flowing from positive DAC
output when the digital input code is set to zero. Offset
error is expressed in LSBs.
A gain error is the difference between the ideal and the
actual full-scale output current on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step. The ideal current is
defined by reference voltage at V
Static Performance Parameter Definitions
Intermodulation Distortion (IMD)
Dual, 10-Bit, 80Msps, Current-Output DAC
______________________________________________________________________________________
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
REFO
/ I
REF
Offset Error
Gain Error
x 32.
The settling time is the amount of time required from the
start of a transition until the DAC output settles to its
new output value to within the converter’s specified
accuracy.
A glitch is generated when a DAC switches between
two codes. The largest glitch is usually generated
around the midscale transition, when the input pattern
transitions from 011…111 to 100…000. This occurs due
to timing variations between the bits. The glitch impulse
is found by integrating the voltage of the glitch at the
midscale transition over time. The glitch impulse is usu-
ally specified in pV-s.
TRANSISTOR COUNT: 9,035
PROCESS: CMOS
Table 4. Part Selection Table
MAX5851
MAX5852
MAX5853
MAX5854
PART
SPEED (Msps)
165
165
80
80
Chip Information
Glitch Impulse
RESOLUTION
Settling Time
10-bit, dual
10-bit, dual
8-bit, dual
8-bit, dual
17

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