MCP4821-E/P Microchip Technology, MCP4821-E/P Datasheet - Page 19
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MCP4821-E/P
Manufacturer Part Number
MCP4821-E/P
Description
IC DAC 12BIT W/SPI 8DIP
Manufacturer
Microchip Technology
Specifications of MCP4821-E/P
Number Of Converters
1
Package / Case
8-DIP (0.300", 7.62mm)
Settling Time
4.5µs
Number Of Bits
12
Data Interface
Serial, SPI™
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 125°C
Mounting Type
Through Hole
Resolution
12 bit
Interface Type
Serial (3-Wire, SPI, Microwire)
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power Dissipation (max)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCP4821-E/P
Manufacturer:
MICROCHIP
Quantity:
3 400
6.0
The MCP482X devices are general purpose DACs
intended to be used in applications where a precision,
low-power DAC with moderate bandwidth and internal
voltage reference is required.
Applications generally suited for the MCP482X devices
include:
• Set Point or Offset Trimming
• Sensor Calibration
• Precision Selectable Voltage Reference
• Portable Instrumentation (Battery-Powered)
• Calibration of Optical Communication Devices
6.1
The MCP482X devices utilize a 3-wire synchronous
serial protocol to transfer the DACs’ setup and output
values from the digital source. The serial protocol can
be interfaced to SPI™ or Microwire peripherals com-
mon on many microcontroller units (MCUs), including
Microchip’s PICmicro
of MCUs. In addition to the three serial connections
(CS, SCK and SDI), the LDAC signal synchronizes
when the serial settings are latched into the DAC’s
output from the serial input latch. Figure 6-1 illustrates
the required connections. Note that LDAC is active-low.
If desired, this input can be tied low to reduce the
required connections from 4 to 3. Write commands will
be latched directly into the output latch when a valid 16
clock transmission has been received and CS has
been raised.
6.2
The typical application will require a bypass capacitor
in order to filter high-frequency noise. The noise can be
induced onto the power supply's traces or as a result of
changes on the DAC's output. The bypass capacitor
helps to minimize the effect of these noise sources on
signal integrity. Figure 6-1 illustrates an appropriate
bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close to the device power pin (V
4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has sep-
arate digital and analog power supplies, AV
AV
© 2005 Microchip Technology Inc.
SS
should reside on the analog plane.
TYPICAL APPLICATIONS
Digital Interface
Power Supply Considerations
®
MCUs and dsPIC
DD
) as possible (within
®
DSC family
DD
and
6.3
The voltage noise density (in µV/ Hz) is illustrated in
Figure 2-9. This noise appears at V
rily a result of the internal reference voltage. Its 1/f
corner (f
Figure 2-10 illustrates the voltage noise (in mV
mV
effective method to produce a single-pole Low-Pass
Filter (LPF) that will reduce this noise. For instance, a
bypass capacitor sized to produce a 1 kHz LPF would
result in an E
necessary when trying to achieve the low DNL
performance (at G = 1) that the MCP482X devices are
capable of. The tested range for stability is .001µF thru
4.7 µF.
FIGURE 6-1:
Diagram.
6.4
Inductively-coupled AC transients and digital switching
noise can degrade the output signal integrity,
potentially
performance. Careful board layout will minimize these
effects and increase the Signal-to-Noise Ratio (SNR).
Bench testing has shown that a multi-layer board
utilizing a low-inductance ground plane, isolated inputs,
isolated outputs and proper decoupling are critical to
achieving the performance that the MCP482X devices
are
environments may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
1 µF
0.1 µF
V
V
OUTA
OUTB
P-P
MCP4821/MCP4822
capable
). A small bypass capacitor on V
CORNER
Output Noise Considerations
Layout Considerations
V
AV
DD
SS
NREF
masking
) is approximately 400 Hz.
1 µF
SDI
of
V
V
of about 100 µV
OUTA
OUTB
providing.
Typical Connection
V
AV
the
DD
SS
0.1 µF 0.1 µF
SDI
MCP482X
Particularly
OUTX
RMS
DS21953A-page 19
LDAC
. This would be
SDO
, and is prima-
SCK
CS
CS
OUTX
1
0
V
AV
family’s
RMS
DD
harsh
is an
SS
or