CS4341A-KSZ Cirrus Logic Inc, CS4341A-KSZ Datasheet - Page 13

• Manufacturer Part Number: CS4341A-KSZ
• Description: IC DAC STER 24BIT 192KHZ 16SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4341A-KSZ

• Package / Case: 16-SOIC
• Number Of Bits: 24
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 90mW
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Conversion Rate: 192 KSPS
• Resolution: 24 bit
• Interface Type: Serial
• Operating Supply Voltage: 3.3 V or 5 V
• Operating Temperature Range: + 70 C
• Maximum Power Dissipation: 125 mW
• Mounting Style: SMD/SMT
• Number Of Dac Outputs: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1633

DS582F2
3.9.3b
To read from the device, follow the procedure below while adhering to the control port
Switching Specifications.
1) Initiate a START condition to the I
must be 001000. The seventh bit must match the setting of the AD0 pin, and the eighth must
be 1. The eighth bit of the address byte is the R/W bit.
2) After transmitting an acknowledge (ACK), the device will then transmit the contents of
the register pointed to by the MAP. The MAP register will contain the address of the last
register written to the MAP, or the default address (see section 3.9.2) if an I
first operation performed on the device.
3) Once the device has transmitted the contents of the register pointed to by the MAP, issue
an ACK.
4) If the INCR bit is set to 1, the device will continue to transmit the contents of successive
registers. Continue providing a clock and issue an ACK after each byte until all the desired
registers are read, then initiate a STOP condition to the bus.
5) If the INCR bit is set to 0 and further I
essary to initiate a repeated START condition and follow the procedure detailed from step
1. If no further reads from other registers are desired, initiate a STOP condition to the bus.
S D A
S C L
N O TE : If operation is a w rite, this byte contains the M em ory A ddress P ointer, M A P . If
operation is a read, this byte contains the data of the register pointed to by the M A P .
S ta rt
I
2
C Read
0 01 0 00
Figure 7. Control Port Timing, I
AD 0
R /W
A C K
2
C bus followed by the address byte. The upper 6 bits
D AT A
1-8
2
C reads from other registers are desired, it is nec-
N O TE
A C K
2
C Mode
D A TA
1-8
A C K
Stop
CS4341A
2
C read is the
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