AD5504BRUZ Analog Devices Inc, AD5504BRUZ Datasheet - Page 6

• Manufacturer Part Number: AD5504BRUZ
• Description: IC DAC 12BIT SPI 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5504BRUZ

• Data Interface: SPI™, QSPI™, MICROWIRE™, and DSP
• Design Resources: Powering a 30V DAC from a 3V supply (CN0193)
• Settling Time: 45µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Input Channel Type: Serial
• Supply Voltage Range - Analogue: 10V To 62V
• Supply Voltage Range - Digital: 2.3V To 5.5V
• Supply Current: 2mA
• Digital Ic: RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5504
TIMING CHARACTERISTICS
V
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
Maximum SCLK frequency is 16.667 MHz.
Under load conditions shown in Figure 2.
Time from when the V
Time required from execution of power-on software command to when the DAC outputs have settled to 1 V.
DD
2
3
3
4
5
= 30 V, V
LOGIC
= 2.3 V to 5.5 V and −40°C < T
DD
/V
LOGIC
Limit
60
10
10
30
15
5
0
20
20
50
15
100
20
110
55
25
50
50
5
supplies are powered-up to when a digital interface command can be executed.
1
TO OUTPUT
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
μs typ
ns min
ns max
ns min
μs max
μs max
μs typ
PIN
A
Figure 2. Load Circuit for SDO Timing Diagram
< +105°C; all specifications T
50pF
C
DD
L
) and timed from a voltage level of (V
200µA
200µA
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width low
SCLK falling edge to LDAC rising edge
CLR pulse width low
CLR pulse activation time
ALARM clear time
SCLK cycle time in read mode
SCLK rising edge to SDO valid
SCLK to SDO data hold time
Power-on reset time (this is not shown in the timing diagrams)
Power-on time (this is not shown in the timing diagrams)
ALARM clear to output amplifier turn on (this is not shown in the timing
diagrams)
Rev. A | Page 6 of 20
I
I
OL
OH
V
OH
(MIN) – V
MIN
2
to T
OL
IL
(MAX)
MAX
+ V
, unless otherwise noted.
IH
)/2.