MAX5156BCEE+ Maxim Integrated Products, MAX5156BCEE+ Datasheet - Page 11

• Manufacturer Part Number: MAX5156BCEE+
• Description: IC DAC DUAL 5VOLT 12BIT 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5156BCEE+

• Settling Time: 15µs
• Number Of Bits: 12
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 667mW
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Resolution: 12 bit
• Interface Type: Serial (SPI)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Supply Current: 0.65 mA
• Voltage Reference: External
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2. Connections for Microwire
Figure 3. Connections for SPI/QSPI
Figure 4. Serial-Data Format
MSB...................................................................................LSB
Address Bits
1 Address/2 Control Bits
Low-Power, Dual, 12-Bit Voltage-Output DACs
A0
MAX5156
MAX5157
MAX5156
MAX5157
Control Bits
SCLK
______________________________________________________________________________________
SCLK
16 Bits of Serial Data
C1, C0
DIN
DIN
CS
CS
MSB...DataBits...LSB
D11.......................D0
12 Data Bits
CPOL = 0, CPHA = 0
SK
SO
I/O
MOSI
SCK
I/O
MICROWIRE
SPI/QSPI
PORT
PORT
V
SS
CC
Sub
Bit
S0
0
with Configurable Outputs
The MAX5156/MAX5157’s digital inputs are double
buffered, which allows any of the following: loading the
input register(s) without updating the DAC register(s),
updating the DAC register(s) from the input register(s),
or updating the input and DAC registers concurrently.
The address and control bits allow the DACs to act
independently.
Send the 16-bit data as one 16-bit word (QSPI) or two
8-bit packets (SPI, Microwire), with CS low during this
period. The address and control bits determine which
register will be updated, and the state of the registers
when exiting shutdown. The 3-bit address/control
determines the following:
The general timing diagram in Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
DOUT is the internal shift register’s output. It allows for
daisy-chaining and data readback. The MAX5156/
MAX5157 can be programmed to shift data out of
DOUT on SCLK’s falling edge (Mode 0) or rising edge
(Mode 1). Mode 0 provides a lag of 16 clock cycles,
which maintains compatibility with SPI/QSPI and
Microwire interfaces. In Mode 1, the output data lags
15.5 clock cycles. On power-up, the device defaults to
Mode 0.
UPO allows an external device to be controlled through
the MAX5156/MAX5157 serial interface (Table 1), there-
by reducing the number of microcontroller I/O pins
required. On power-up, UPO is low.
PDL disables software shutdown when low. When in
shutdown, transitioning PDL from high to low wakes up
the part with the output set to the state prior to shut-
down. PDL can also be used to asynchronously wake
up the device.
registers to be updated
clock edge on which data is clocked out via the seri-
al data output (DOUT)
state of the user-programmable logic output
configuration of the device after shutdown
User-Programmable Logic Output (UPO)
Power-Down Lockout Input
Serial Data Output (DOUT)
(PDL)
11