MAX5152BEEE+ Maxim Integrated Products, MAX5152BEEE+ Datasheet - Page 11

• Manufacturer Part Number: MAX5152BEEE+
• Description: IC DAC 13BIT DUAL LP SER 16-QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX5152BEEE+

• Settling Time: 20µs
• Number Of Bits: 13
• Data Interface: Serial
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 667mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2. Connections for Microwire
Figure 3. Connections for SPI/QSPI
Figure 4. Serial-Data Format
MSB ..................................................................................LSB
Address Bits
1 Address/2 Control Bits
Low-Power, Dual, 13-Bit Voltage-Output DACs
MAX5152
MAX5153
A0
MAX5152
MAX5153
SCLK
Control Bits
SCLK
DIN
CS
______________________________________________________________________________________
DIN
16 Bits of Serial Data
C1, C0
CS
MSB.......Data Bits.........LSB
D12.................................D0
CPOL = 0, CPHA = 0
MOSI
SCK
I/O
SK
SO
I/O
13 Data Bits
MICROWIRE
SPI/QSPI
PORT
PORT
V
SS
CC
with Configurable Outputs
Send the 16-bit data as two 8-bit packets (SPI,
Microwire) or one 16-bit word (QSPI), with CS low dur-
ing this period. The address and control bits determine
which register will be updated, as well as the state of
the registers when exiting shutdown. The 3-bit
address/control determines:
The general timing diagram in Figure 5 illustrates how
data is acquired. Driving CS low enables the device to
receive data. Otherwise, the interface control circuitry is
disabled. With CS low, data at DIN is clocked into the
register on the rising edge of SCLK. As CS goes high,
data is latched into the input and/or DAC registers
depending on the address and control bits. The maxi-
mum clock frequency guaranteed for proper operation
is 10MHz. Figure 6 depicts a more detailed timing dia-
gram of the serial interface.
DOUT is the internal shift register’s output. It allows for
daisy-chaining and data readback. The MAX5152/
MAX5153 can be programmed to shift data out of
DOUT on SCLK’s falling edge (Mode 0) or rising edge
(Mode 1). Mode 0 provides a lag of 16 clock cycles,
which maintains compatibility with SPI/QSPI and
Microwire interfaces. In Mode 1, the output data lags
15.5 clock cycles. On power-up, the device defaults to
Mode 0.
UPO allows an external device to be controlled through
the MAX5152/MAX5153 serial interface (Table 1), there-
by reducing the number of microcontroller I/O pins
required. On power-up, UPO is low.
PDL disables software shutdown when low. When in
shutdown, transitioning PDL from high to low wakes up
the part with the output set to the state prior to shut-
down. PDL can also be used to asynchronously wake
up the device.
Any number of MAX5152/MAX5153s can be daisy
chained by connecting the DOUT pin of one device to
the DIN pin of the following device in the chain (Figure
7).
registers to be updated
clock edge on which data is clocked out via the seri-
al data output (DOUT)
state of the user-programmable logic output
configuration of the device after shutdown
User-Programmable Logic Output (UPO)
Power-Down Lockout Input
Serial Data Output (DOUT)
Daisy Chaining Devices
(PDL)
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