LTC1669CMS8#TRPBF Linear Technology, LTC1669CMS8#TRPBF Datasheet - Page 10
![IC DAC 10BIT R-R I2C 8-MSOP](/photos/6/57/65743/8-msop_05-08-1660_sml.jpg)
LTC1669CMS8#TRPBF
Manufacturer Part Number
LTC1669CMS8#TRPBF
Description
IC DAC 10BIT R-R I2C 8-MSOP
Manufacturer
Linear Technology
Datasheet
1.LTC1669CMS8PBF.pdf
(16 pages)
Specifications of LTC1669CMS8#TRPBF
Settling Time
30µs
Number Of Bits
10
Data Interface
I²C
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
630µW
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
APPLICATIONS INFORMATION
LTC1669
Slave Address (SOT-23 Package)
The slave address for the SOT-23 package has been
factory programmed to be “0100 000” (LTC1669) and
“0100 001” (LTC1669-1). If another address is required,
please consult the factory.
Command Byte
The stop condition normally initiates the update of the
DAC’s output latches. Simultaneous update of more than
one DAC or other devices on the bus can be achieved by
reissuing new start bit, address, command and data bytes
before issuing a fi nal stop condition (which will update
all the devices). An alternate way to achieve simultaneous
LTC1669 updates is to override the stop condition update
by setting the “SY” bit of the command byte. Setting this
bit sets the device to update the DAC output latches only
at the reception of a SYNC address quick command. The
actual update occurs on the rising edge of SCL during the
Acknowledge. In this way, all devices can update on the
reception of the SYNC address quick command instead
of the STOP condition.
A Shutdown (SD) bit = HIGH will put the device in a low
power state but retain all data latch information. Shutdown
will occur at the reception of a STOP condition. This way
shutdown could be synchronized to other devices. The
output impedance of the DAC will go to a high impedance
state (≈ 500kΩ to GND).
10
SY
SD
BG
7
X
X
X
1
0
1
0
1
0
X
6
Allows update on Acknowledge of SYNC Address only
Update on Stop condition only (Power-On Default)
Puts the device in power-down mode
Puts the device in standard operating mode
(Power-On Default)
Selects the internal bandgap reference
Selects the supply as the reference (Power-On Default)
Don’t Care
5
X
4
X
X
3
BG
2
SD
1
SY
0
The Bandgap (BG) bit when set to “0” selects the DAC
supply voltage as its voltage reference. The full-scale
output of the DAC with this setting is equal to the supply
voltage. When the BG bit is set to “1,” the internal bandgap
reference (≈1.25V) is selected as the DAC’s reference. The
full-scale output voltage for this setting is 2.5V.
Data Bytes
Least Signifi cant Data Byte
Most Signifi cant Data Byte
X = Don’t care
Send Byte Protocol
The Send Byte protocol used on the LTC1669 is actually a
subset of the Write Word protocol described previously.
The Send Byte protocol can only be used to send the
command byte information to the LTC1669.
The Send Byte protocol is also used whenever the Write
Word protocol is interrupted for any reason. Reception of
a START or STOP condition after the Acknowledge of the
command byte, but before the Acknowledge of the last
data byte, will cause both data bytes to be ignored and
the command byte to be accepted.
Reception of a START or STOP condition before the Ac-
knowledge of the command byte will cause the interrupted
command byte to be ignored.
D7
7
7
X
S = Start Condition, Wr = Write Bit, A = Acknowledge, P = Stop Condition
S
1
D6
6
6
X
Slave Address
7
D5
X
5
5
Wr
1
D4
4
X
4
A
1
Command Byte
D3
3
X
3
8
D2
2
2
X
A
1
P
D1
1
D9
1
1
1669 TA04
D0
D8
0
0
1669fa