LTC1668IG#PBF Linear Technology, LTC1668IG#PBF Datasheet - Page 15

• Manufacturer Part Number: LTC1668IG#PBF
• Description: IC D/A CONV 16BIT 50MSPS 28-SSOP
• Manufacturer: Linear Technology

Specifications of LTC1668IG#PBF

• Settling Time: 20ns
• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 180mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Resolution (bits): 16bit
• Sampling Rate: 50MSPS
• Input Channel Type: Parallel
• Supply Voltage Range - Analog: ± 4.75V To ± 5.25V
• Supply Current: 33mA
• Digital Ic Case Style: SSOP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

APPLICATIO S I FOR ATIO
Resistor Loaded Outputs
A differential resistor loaded output configuration is shown
in Figure 6. It is simple and economical, but it can drive
only differential loads with impedance levels and ampli-
tudes appropriate for the DAC outputs.
The recommended single-ended resistor loaded configu-
ration is essentially the same circuit as the differential
resistor loaded, case—simply use the I
referred to ground. Rather than tying the unused I
output to ground, it is preferred to load it with the equiva-
lent R
waveform complementary to I
Op Amp I to V Converter Outputs
Adding an op amp differential to single-ended converter
circuit to the differential resistor loaded output gives the
circuit of Figure 7.
This circuit complements the capabilities of the trans-
former-coupled application at lower frequencies, since
available op amps can deliver good AC distortion perfor-
mance at signal frequencies of a few MHz down to DC. The
optional capacitor adds a single real pole of filtering, and
Figure 7. Differential to Single-Ended Op Amp I-V Converter
LTC1666/
LTC1667/
LTC1668
LOAD
I
I
OUT A
OUT B
Figure 6. Differential Resistor-Loaded Output
of I
60pF
OUT A
LTC1666/
LTC1667/
LTC1668
52.3
I
I
OUT A
OUT B
U
. Then I
52.3
U
200
200
OUT B
52.3
OUT A
500
–
+
W
will still swing with a
.
52.3
LT1809
1666/7/8 F07
500
OUT A
10dBm
1V
U
1666/7/8 F08
output,
V
OUT
OUT B
helps reduce distortion by limiting the high frequency
signal amplitude at the op amp inputs. The circuit swings
Figure 8 shows a simplified circuit for a single-ended
output using I-to-V converter to produce a unipolar
buffered voltage output. This configuration typically has
the best DC linearity performance, but its AC distortion at
higher frequencies is limited by U1’s slewing capabilities.
Digital Interface
The LTC1666/LTC1667/LTC1668 have parallel inputs that
are latched on the rising edge of the clock input. They
accept CMOS levels from either 5V or 3.3V logic and can
accept clock rates of up to 50MHz.
Referring to the Timing Diagram and Block Diagram, the
data inputs go to master-slave latches that update on the
rising edge of the clock. The input logic thresholds, V
2.4V min, V
levels over temperature. The guaranteed setup time, t
is 8ns minimum and the hold time, t
The minimum clock high and low times are guaranteed at
6ns and 8ns, respectively. These specifications allow the
LTC1666/LTC1667/LTC1668 to be clocked at up to 50Msps
minimum.
For best AC performance, the data and clock waveforms
need to be clean and free of undershoot and overshoot.
Clock and data interconnect lines should be twisted pair,
coax or microstrip, and proper line termination is impor-
tant. If the digital input signals to the DAC are considered
as analog AC voltage signals, they are rich in spectral
components over a broad frequency range, usually in-
1V around ground.
LTC1666/LTC1667/LTC1668
LTC1666/
LTC1667/
LTC1668
Figure 8. Single-Ended Op Amp I to V Converter
LADCOM
I
I
OUT A
OUT B
IL
= 0.8V max, work with 3.3V or 5V CMOS
I
10mA
OUTFS
200
–
+
LT
®
U1
200
1812
C
R
OUT
FB
DH
, is 4ns minimum.
V
0V TO 2V
1666/7/8
OUT
F09
15
IH
DS
=
,