AD5306BRUZ-REEL7 Analog Devices Inc, AD5306BRUZ-REEL7 Datasheet - Page 6

• Manufacturer Part Number: AD5306BRUZ-REEL7
• Description: IC DAC 8BIT QUAD W/BUFF 16-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5306BRUZ-REEL7

• Settling Time: 6µs
• Number Of Bits: 8
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 4.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5306/AD5316/AD5326
TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
C
1
2
3
4
1
2
3
4
5
6
7
8
9
10
11
12
13
See Figure 2.
Guaranteed by design and characterization; not production tested.
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
falling edge.
C
B
DD
3
4
B
is the total capacitance of one bus line in pF. t
= 2.5 V to 5.5 V; all specifications T
SDA
SCL
LDAC
LDAC
NOTES
1
2
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
2
1
2
START
CONDITION
t
9
Limit at T
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1C
20
400
400
t
4
A, B Versions
t
B
3
MIN
4
1
, T
MAX
MIN
R
t
10
and t
t
6
to T
F
measured between 0.3 V
MAX
Figure 2. 2-Wire Serial Interface Timing Diagram
, unless otherwise noted.
Unit
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
pF max
t
2
t
11
Rev. F | Page 6 of 24
t
5
DD
and 0.7 V
REPEATED START
CONDITION
Conditions/Comments
SCL cycle time
t
t
t
t
t
t
t
t
t
t
t
t
t
t
LDAC pulse width
SCL rising edge to LDAC rising edge
Capacitive load for each bus line
HIGH
LOW
HD,STA
SU,DAT
HD,DAT
SU,STA
SU,STO
BUF
R
R
F
F
F
F
, fall time of SDA when transmitting
, fall time of SDA when receiving (CMOS compatible)
, fall time of SCL and SDA when receiving
, fall time of SCL and SDA when transmitting
, rise time of SCL and SDA when receiving
, rise time of SCL and SDA when receiving (CMOS compatible)
, bus free time between a stop and a start condition
, SCL low time
, SCL high time
DD
t
7
, setup time for repeated start
, stop condition setup time
, start/repeated start condition hold time
, data setup time
, data hold time
.
IH
t
min of the SCL signal) to bridge the undefined region of SCL’s
4
t
1
t
12
t
13
STOP
CONDITION
t
8
t
12