AD5340BRUZ Analog Devices Inc, AD5340BRUZ Datasheet - Page 7
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AD5340BRUZ
Manufacturer Part Number
AD5340BRUZ
Description
IC DAC 12BIT SNGL VOUT 24-TSSOP
Manufacturer
Analog Devices Inc
Specifications of AD5340BRUZ
Data Interface
Parallel
Settling Time
8µs
Number Of Bits
12
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
1.25mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resolution (bits)
12bit
Sampling Rate
125kSPS
Input Channel Type
Parallel
Supply Voltage Range - Analogue
2.5V To 5.5V
Supply Current
140µA
Digital Ic Case Style
TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AD5340BRUZ
Manufacturer:
Analog Devices Inc
Quantity:
135
Part Number:
AD5340BRUZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. AD5330 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13 to 20
LDAC
GAIN
BUF
CLR
DB
DB
WR
CS
. .
Mnemonic
BUF
NC
V
V
GND
CS
WR
GAIN
CLR
LDAC
PD
V
DB
7
0
REF
OUT
DD
20
13
10
1
8
6
7
9
0
to DB
7
RESET
Gain Control Pin. This controls whether the output range from the DAC is 0 V to V
Description
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
No Connect.
Reference Input.
Output of DAC. Buffered output with rail-to-rail operation.
Ground reference point for all circuitry on the part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
Asynchronous active low control input that clears all input registers and DAC registers to zero.
Active low control input that updates the DAC registers with the contents of the input registers.
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Eight Parallel Data Inputs. DB
POWER-ON
REGISTER
RESET
INPUT
Figure 3. AD5330 Functional Block Diagram
REGISTER
DAC
8-BIT
V
DAC
REF
7
3
is the MSB of these eight bits.
Rev. A | Page 7 of 28
BUFFER
AD5330
V
POWER-DOWN
12
DD
LOGIC
PD
11
GND
5
4
V
AD5330/AD5331/AD5340/AD5341
OUT
LDAC
Figure 4. AD5330 Pin Configuration
GAIN
V
V
GND
BUF
CLR
OUT
REF
REF
WR
NC
CS
or 0 V to 2 × V
10
1
2
3
4
5
6
7
8
9
NC = NO CONNECT
(Not to Scale)
AD5330
TOP VIEW
8-BIT
REF
.
20
19
18
17
16
15
14
13
12
11
DB
DB
DB
DB
DB
DB
DB
DB
V
PD
DD
7
6
5
4
3
2
1
0