AD9740ARURL7 Analog Devices Inc, AD9740ARURL7 Datasheet
AD9740ARURL7
Specifications of AD9740ARURL7
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AD9740ARURL7 Summary of contents
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FEATURES High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SNR @ 5 MHz output, 125 MSPS Twos complement or straight binary data format Differential current outputs Power dissipation: ...
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AD9740 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 DC Specifications ......................................................................... 4 Dynamic Specifications ............................................................... 5 Digital Specifications ................................................................... 6 ...
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REVISION HISTORY 12/05—Rev Rev. B Updated Format.................................................................. Universal Changes to General Description and Product Highlights...........1 Changes to Table 1 ............................................................................4 Changes to Table 2 ............................................................................5 Changes to Table 5 ............................................................................8 Changes to Figure 6.........................................................................10 Inserted Figure 11; Renumbered ...
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AD9740 SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset ...
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DYNAMIC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLOCK 1 Output Settling ...
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AD9740 Parameter Multitone Power Ratio (8 Tones at 400 kHz Spacing MSPS 15.0 MHz to 18.2 MHz CLOCK OUT 0 dBFS Output −6 dBFS Output −12 dBFS Output −18 dBFS Output 1 Measured single-ended into ...
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ABSOLUTE MAXIMUM RATINGS Table 4. With Parameter Respect to Min AVDD ACOM −0.3 DVDD DCOM −0.3 CLKVDD CLKCOM −0.3 ACOM DCOM −0.3 ACOM CLKCOM −0.3 DCOM CLKCOM −0.3 AVDD DVDD −3.9 AVDD CLKVDD −3.9 DVDD CLKVDD −3.9 CLOCK, SLEEP DCOM ...
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AD9740 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS (MSB) DB9 1 DB8 2 DB7 3 DB6 4 DB5 5 AD9740 DB4 6 DB3 TOP VIEW 7 (Not to Scale) DB2 8 DB1 9 DB0 ...
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TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or ...
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AD9740 TYPICAL PERFORMANCE CHARACTERISTICS 95 210MSPS (LFCSP) 90 125MSPS 65MSPS 70 125MSPS (LFCSP 210MSPS (MHz) OUT Figure 6. SFDR vs dBFS OUT ...
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A (dBFS) OUT Figure 12. Single-Tone SFDR vs OUT OUT 125MSPS 80 210MSPS (LFCSP) 75 ...
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AD9740 34MHz 60 49MHz 55 50 –40 – TEMPERATURE (°C) Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 1 ...
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FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9740. The AD9740 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing ...
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AD9740 REFLO 150pF 1.2V REF REFIO CURRENT SOURCE FS ADJ REFERENCE AD9740 CONTROL AMPLIFIER Figure 25. External Reference Configuration REFERENCE CONTROL AMPLIFIER The AD9740 contains a control amplifier that is used to regulate the full-scale output current The ...
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These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the ...
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AD9740 In the differential input mode, the clock input functions as a high impedance differential pair. The common-mode level of the CLK+ and CLK− inputs can vary from 0. 2.25 V, and the differential voltage can be as ...
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I (mA) OUTFS Figure 29. I vs. I AVDD OUTFS 20 18 210MSPS 16 14 165MSPS 12 10 125MSPS 8 6 65MSPS 0.01 ...
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AD9740 The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (that is, V swing ...
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C OPT R FB 200Ω 10mA AD9740 OUTFS IOUTA 22 U1 IOUTB 21 200Ω Figure 36. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ...
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AD9740 EVALUATION BOARD GENERAL DESCRIPTION The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC product in the SOIC and LFCSP packages. Careful attention to layout and circuit design, combined with a prototyping area, allows the ...
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AVDD + C14 C16 C17 10μF 0.1μF 0.1μF 16V DVDD + C15 C18 C19 10μF 0.1μF 0.1μF 16V CKEXT CLOCK JP4 1 28 DB13 CLOCK DB13 2 27 DB12 DVDD DB12 DVDD 3 26 DB11 DCOM DB11 4 25 DB10 ...
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AD9740 Figure 41. SOIC Evaluation Board—Primary Side Figure 42. SOIC Evaluation Board—Secondary Side Rev Page ...
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Figure 43. SOIC Evaluation Board—Ground Plane Figure 44. SOIC Evaluation Board—Power Plane Rev Page AD9740 ...
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AD9740 Figure 45. SOIC Evaluation Board Assembly—Primary Side Figure 46. SOIC Evaluation Board Assembly—Secondary Side Rev Page ...
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L1 BEAD TB1 1 BLK C2 C3 10μF 0.1μF TP2 6.3V TB1 2 L2 BEAD TB3 1 BLK C7 C4 0.1μF 10μF TP4 6.3V TB3 2 L3 BEAD TB4 1 BLK C9 C5 0.1μF 10μF TP6 6.3V TB4 2 R3 ...
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AD9740 32 1 DB7 DB8 DB7 2 31 DB6 DB9 DB6 30 3 DVDD DB10 DVDD 4 29 DB5 DB11 DB5 5 28 DB4 DB12 DB4 27 6 DB3 DB13 DB3 7 26 DB2 DCOM1 DB2 25 8 DB1 SLEEP ...
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Figure 50. LFCSP Evaluation Board Layout—Primary Side Figure 51. LFCSP Evaluation Board Layout—Secondary Side Rev Page AD9740 ...
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AD9740 Figure 52. LFCSP Evaluation Board Layout—Ground Plane Figure 53. LFCSP Evaluation Board Layout—Power Plane Rev Page ...
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Figure 54. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 55. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev Page AD9740 ...
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AD9740 OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC ...
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... AD9740ARRL −40°C to +85°C 1 AD9740ARZ −40°C to +85°C 1 AD9740ARZRL −40°C to +85°C AD9740ARU −40°C to +85°C AD9740ARURL7 −40°C to +85°C 1 AD9740ARUZ −40°C to +85°C 1 AD9740ARUZRL7 −40°C to +85°C AD9740ACP −40°C to +85°C AD9740ACPRL7 − ...
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AD9740 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02911–0–12/05(B) Rev Page ...