AD5024BRUZ Analog Devices Inc, AD5024BRUZ Datasheet - Page 8

• Manufacturer Part Number: AD5024BRUZ
• Description: IC DAC QUAD 12BIT 1LSB 16-TSSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5024BRUZ

• Data Interface: SPI™
• Settling Time: 8µs
• Number Of Bits: 12
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 30mW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TSSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 4.5V To 5.5V
• Supply Current: 4mA
• Digital Ic Case Style: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5024/AD5044/AD5064
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
LDAC
SYNC
V
V
V
POR
V
SDO
CLR
V
V
GND
DIN
SCLK
DD
OUT
OUT
REFIN
OUT
OUT
A
C
D
B
Description
LDAC can be operated in two modes, asynchronously and synchronously, as shown in
this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows
all DAC outputs to simultaneously update. This pin can also be tied permanently low in standalone mode.
When daisy-chain mode is enabled, this pin cannot be tied permanently low; the
used in asynchronous LDAC update mode, as shown in
high after pulsing.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes
low, it powers on the SCLK and DIN buffers and enables the shift register. Data is transferred in on the
falling edges of the next 32 clocks. If SYNC is taken high before the 32
SYNC acts as an interrupt and the write sequence is ignored by the device.
Power Supply Input. These parts can be operated from 4.5 V to 5.5 V, and the supply should be decoupled
with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to V
powers up all four DACs to midscale.
This is a common pin for reference input for DAC A, DAC B, DAC C, and DAC D.
Serial Data Output. Can be used to daisy-chain a number of AD5064-1 devices together. The serial data
is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are
ignored. When CLR is activated, the input register and the DAC register are updated with the data
contained in the clear code register—zero, midscale, or full scale. Default setting clears the output to 0 V.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the shift register on the
falling edge of the serial clock input.
Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data
can be transferred at rates of up to 50 MHz.
V
V
V
LDAC
SYNC
OUT
OUT
REFIN
POR
V
Figure 6. 14-Lead TSSOP (RU-14)
DD
A
C
1
2
3
4
5
6
7
Rev. D | Page 8 of 28
(Not to Scale)
AD5064-1
TOP VIEW
14
13
12
11
10
9
8
SCLK
DIN
GND
V
V
CLR
SDO
OUT
OUT
B
D
Figure 5
, and the
nd
falling edge, the rising edge of
LDAC pin must be brought
LDAC pin should be
Figure 4
. Pulsing
DD