AD5322BRMZ Analog Devices Inc, AD5322BRMZ Datasheet - Page 5

• Manufacturer Part Number: AD5322BRMZ
• Description: IC DAC 12BIT DUAL 10MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5322BRMZ

• Data Interface: Serial
• Settling Time: 6µs
• Number Of Bits: 12
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 2.5mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 12bit
• Sampling Rate: 125kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.5V To 5.5V
• Supply Current: 300µA
• Digital Ic Case Style: SOP
• Package: 10MSOP
• Resolution: 12 Bit
• Conversion Rate: 125 KSPS
• Architecture: Resistor-String
• Digital Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Number Of Outputs Per Chip: 2
• Output Type: Voltage
• Full Scale Error: ±1 %FSR
• Integral Nonlinearity Error: ±8 LSB
• Maximum Settling Time: 10 us
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
V
Table 3.
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
3
1
2
3
4
5
6
7
8
9
10
Guaranteed by design and characterization, not production tested.
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
See Figure 2.
DD
= 2.5 V to 5.5 V, all specifications T
SYNC
LDAC
LDAC
SCLK
1
DIN
SEE INPUT SHIFT REGISTER SECTION.
1
Limit at T
33
13
13
0
5
4.5
0
100
20
20
t
8
MIN
DB15
MIN
, T
t
6
t
MAX
to T
4
t
5
(A, B Version)
MAX
, unless otherwise noted.
Figure 2. Serial Interface Timing Diagram
t
DD
3
) and timed from a voltage level of (V
t
Rev. C | Page 5 of 24
1
t
2
DB0
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t
7
1, 2, 3
t
10
Conditions/Comments
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Active Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
LDAC Pulse Width
SCLK Falling Edge to LDAC Rising Edge
IL
+ V
IH
t
)/2.
9
AD5302/AD5312/AD5322