AD9116BCPZ Analog Devices Inc, AD9116BCPZ Datasheet - Page 39

• Manufacturer Part Number: AD9116BCPZ
• Description: IC DAC DUAL 12BIT LO PWR 40LFCSP
• Manufacturer: Analog Devices Inc
• Series: TxDAC®r

Specifications of AD9116BCPZ

• Data Interface: Serial
• Number Of Bits: 12
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 232mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 40-LFCSP
• Resolution (bits): 12bit
• Sampling Rate: 125MSPS
• Input Channel Type: Serial
• Supply Current: 55mA
• Digital Ic Case Style: CSP
• No. Of Pins: 40
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Register
Memory R/W
CLKMODE
Version
Address
0x12
0x14
0x1F
Bit
7
6
4
3
2
1
0
7:6
4
3
2
1:0
7:0
Name
CALRSTQ
CALRSTI
CALEN
SMEMWR
SMEMRD
UNCALQ
UNCALI
CLKMODEQ[1:0]
Searching
Reacquire
CLKMODEN
CLKMODEI[1:0]
Version[7:0]
Description
0 (default): no action.
1: clears CALSTATQ.
0 (default): no action.
1: clears CALSTATI.
0 (default): no action.
1: initiates device self-calibration.
0 (default): no action.
1: writes to static memory (calibration coefficients).
0 (default): no action.
1: reads from static memory (calibration coefficients).
0 (default): no action.
1: resets Q DAC calibration coefficients to default (uncalibrated).
0 (default): no action.
1: resets I DAC calibration coefficients to default (uncalibrated).
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retime.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Datapath retimer status bit.
0 (default): clock relationship established.
1: indicates that the internal datapath retimer is searching for clock relationship
(device output is not usable while this bit is high).
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read
back in CLKMODEI[1:0] and CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship
between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Hardware version of the device. This register is set to 0x09 for the latest version of
the device.
Rev. A | Page 39 of 80
AD9114/AD9115/AD9116/AD9117