DJLXT6155LE.B2 Cortina Systems Inc, DJLXT6155LE.B2 Datasheet
DJLXT6155LE.B2
Specifications of DJLXT6155LE.B2
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DJLXT6155LE.B2 Summary of contents
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Cortina Systems SDH/SONET/ATM Transceiver Datasheet ® The Cortina Systems LXT6155 155 Mbps SDH/SONET/ATM Transceiver (LXT6155 Transceiver high speed fully integrated transceiver designed for 155 Mbps SDH/SONET/ATM transmission system applications. The LXT6155 Transceiver provides a LVPECL interface for fiber ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 *Other names and brands may be claimed as the property of others. ® Cortina Systems LXT6155 155 Mbps SDH/SONET/ATM Transceiver © Cortina Systems, Inc. 2007 Legal Disclaimer Page 2 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Contents 1.0 LXT6155 Transceiver Block Diagram........................................................................................... 8 2.0 Pin Assignments and Signal Descriptions.................................................................................. 9 3.0 Functional Description................................................................................................................14 3.1 Transmitter..........................................................................................................................14 3.1.1 Transmitted Signal .................................................................................................15 3.1.1.1 Fiber Based G.957/GR-253 Transmission Systems ..............................15 3.1.2 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 5.0 Application Information ..............................................................................................................34 5.1 Fiber Optic Module Interface ..............................................................................................34 5.2 Coax Interface ....................................................................................................................35 6.0 Test Specifications ......................................................................................................................38 7.0 Mechanical Specifications ..........................................................................................................50 Figures 1 LXT6155 Transceiver Block Diagram .............................................................................................. 8 2 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 8 Primary Control Register Settings, Register #0 (Address A<3:0>=0000)...................................... Control, Register #1 (Address A<3:0>=0001) ..........................................................................28 10 Transmit PLL1, Register #2 (Address A<3:0>=0010)....................................................................29 11 Transmit PLL2, Register #3 (Address A<3:0>=0011)....................................................................29 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Revision History First release of this document from Cortina Systems, Inc. • Table 2, Standards Compliance, on page 15 • Figure 5, Receive Frame Synchronization and Frame Pulse Position, on page ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Formatting change Initial version ® Cortina Systems LXT6155 155 Mbps SDH/SONET/ATM Transceiver Revision 002 Revision Date: 01 July 2002 Revision 001 Revision Date: 01 January 2001 Revision History Page 7 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 1.0 LXT6155 Transceiver Block Diagram Figure 1 shows the block diagram for the LXT6155 Transceiver. Figure 1 LXT6155 Transceiver Block Diagram μP Control (CS, SCLK, SDI, SDO), Hardware (MODE0, SP, CIS, ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 2.0 Pin Assignments and Signal Descriptions Figure 2 LXT6155 Transceiver Pin Assignments XTALIN XTALOUT TAGND TXISH TAVCC TDVCC TSICLKP TSICLKN TPOS TNEG TDGND CS/MODE SCLK/SP SDI/CIS SDO/RIFE TPID7 ® Cortina Systems ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 1 Pin Descriptions (Sheet Pin # Pin Name I/O 1 XTALIN AI/O 2 XTALOUT 3 TAGND S 4 TXISH AI/O 5 TAVCC S 6 TDVCC S 7 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 1 Pin Descriptions (Sheet Pin # Pin Name I/O 15 SDO/RIFE DI/O 16 TPID7/TXTRIM3 17 TPID6/TXTRIM2 DI 18 TPID5/TXTRIM1 19 TPID4/TXTRIM0 20 TPID3/TXTRIMENA DI 21 TPID2 TPID1 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 1 Pin Descriptions (Sheet Pin # Pin Name I/O 36 RSOCLKP DO 37 RSOCLKN 38 PVCC S 39 RNEG DO 40 RPOS 41 RDVCC S 42 RDGND ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 1 Pin Descriptions (Sheet Pin # Pin Name I/O 55 ADDR1/LLIS DI 56 HWSEL DI 57 SUB S 58 WELL S 59 TAGND S 60 TRING0 AO ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.0 Functional Description The LXT6155 Transceiver is a front-end transceiver designed for 155 Mbps OC3/STM1/ ATM transmission applications. Transceiver is compliant. The LXT6155 Transceiver interfaces to either a fiber transceiver or ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.1.1 Transmitted Signal Transmitted signals conform to the standard templates listed in Table 2 Standards Compliance Item Line Rate (Mbps) Line Interface Line Code Signal Templates Jitter 3.1.1.1 Fiber Based G.957/GR-253 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.1.3 Tx Clock Monitoring The LXT6155 Transceiver provides transmit clock monitoring for both serial and parallel operating modes. When using the crystal clock as a reference, the LXT6155 Transceiver monitors the ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 5 Receive Frame Synchronization and Frame Pulse Position RPOCLK RPOD <7:0> ROFP -7 Frame Pulse Position Fh Hex Contents of REG 13h Binary 1111 The clock recovery PLL’s center frequency ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 6 Framing State In Frame 3.2.2.1 Loss of Signal (LOS) Loss of Signal provides an alarm signal indicating incoming signal voltage is weak or incoming data does not contain enough ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.3 Clocks 3.3.1 Parallel Mode The LXT6155 Transceiver accepts TPICLK synchronized with transmit input parallel data TPID<7:0>. The data is serialized and transmitted at TTIP0/TRING0 or TTIP1/TRING1 depending on which line ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.3.3 Crystal Reference Clock (XTALIN/XTALOUT) An optional 19.44 MHz crystal can be connected across the XTALIN and XTALOUT pins. This crystal reference provides an onchip clock that is independent of the ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.5.1 Hardware Mode By setting HWSEL = Low, the LXT6155 Transceiver operates in standalone hardware mode, without a serial microprocessor interface. A subset of the functions available in the Software Mode ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.5.1.1.2 XTAL XTAL is an optional clock, created using an external crystal, connected across the XTALIN and XTALOUT pins. The crystal provides an independent and stable clock source. This clock is ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.5.1.5 Tx Amplitude Trim In Hardware, serial, coax mode, the line driver output amplitude can be controlled via pins 16 to 20. Setting TXTRIMENA (pin #20) high enables the trim capability. ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 9 Software Mode LXT6155 ADDR0, ADDR1 Figure 10 Serial Data Output Word Structure (Read Cycle: R/W=High) CS DON'T SCLK CARE DON'T SDI CARE SDO Figure 11 Serial Data Input Word ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.6 Serial System Interface The serial interface permits the LXT6155 Transceiver to communicate with an Overhead Termination device at 155.52 Mbps. Data and clock lines are differential 3.3 V LVPECL signals. ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 3.8 Loopback Modes The LXT6155 Transceiver provides two loopback modes that can be executed in either hardware or software mode: local loopback and remote loopback. In remote loopback mode, the crystal ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 4.0 Register Definitions There are a total of sixteen (16) control registers in the LXT6155 Transceiver addressed by the lowest four address bits, A<3:0>. See Table 6 Device Address/Control Byte A<6:0> ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 8 Primary Control Register Settings, Register #0 (Address A<3:0>=0000) Bit Default Mnemonic media_sel . ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 . Table 10 Transmit PLL1, Register #2 (Address A<3:0>=0010) Bit Default Mnemonic 7:5 0.1.1 4:3 0.0 2:1 1 Table 11 Transmit PLL2, Register #3 (Address A<3:0>=0011) Bit Default ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 13 Equalizer & AGC, Register #5 (Address A<3:0>=0101) (Sheet Bit Default Mnemonic 3:2 0.0 agc_adapt_gain Table 14 Matching Filter 2, Register #6 (Address ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 17 Rx PLL 2, Register #9 (Address A<3:0>=1001) Bit Default Mnemonic 5:3 0.1.1 freq_det_pw Table 18 Test, Register #10 (Address ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 . Table 20 Rx Digital 1, Register #12 (Address A<3:0>=1100) Bit Default Mnemonic 7 0 los_format 6 1 los_amp_trim 5:4 1 frame_ena ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 . Table 22 Status Control, Register #14 (Address A<3:0>=1110) Bit Default Mnemonic 7:4 0.0.0.0 3:0 0.0.0.0 Table 23 Read-Only Register #15 (Address A<3:0>=1111) Value of: stat_cont bit 7 00 Analog (Status ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 5.0 Application Information The following provides application examples of interfacing the LXT6155 Transceiver to the line side and the overhead terminator side. Line side encoding schemes can be one of two ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 16 3.3 V LVPECL to 3.3 V LVPECL Interface 49 RXISH 330 nF 48 VBIAS 15k 1% 4 TXISH 68 nF Transceiver 47 NC ATST Notes: 1) R1, R2, R5, ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 17 75 Ohm Coax Cable Interface 49 RXISH 330nF 48 VBIAS 15k 1% 47 ATST NC 4 TXISH 68nF . Table 24 Transformer Specifications Parameter Transmission, S12 Return Loss, S11 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 25 Crystal Specifications Parameter Center frequency Freq tolerance Temperature drift Aging Mode Shunt capacitance Equivalent resistance Temperature Range ® Cortina Systems LXT6155 155 Mbps SDH/SONET/ATM Transceiver 5.2 Coax Interface Min ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 6.0 Test Specifications Information in Table 26 Figure 29 on page 49 Transceiver and are guaranteed by test, except as noted by design. Table 26 Absolute Maximum Ratings Parameter DC supply ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 28 DC Electrical Characteristics (Vcc = 3 3 -40 ° °C) (Sheet Parameter Low level output voltage (TTL) Input leakage ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 19 Transmit Serial Input Data Timing TSICLKP TSICLKN TPOS TNEG Table 30 Transmit Analog Characteristics Parameters Transmit jitter generation (Intrinsic jitter SONET spec) Transmit jitter generation (Intrinsic jitter SDH spec) ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 31 Receive Timing Characteristics Parameter Receive serial output clock frequency Receive serial output clock duty cycle Receive serial output clock 2 and data rise/fall time RSOCLKP/RSOCLKN to RPOS/RNEG propagation delay ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 21 Receive Parallel Output Data Timing 1 RPOCLK RPOD<0:7> ROFP 1. Signals shown in HW Mode Mode (HWSEL=1), the RPOCLK polarity can be inverted. Refer to Table 8 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Table 32 Receive Analog Characteristics (Sheet Parameter PLL nominal center frequency PLL capture range PLL track range PLL lock time Equalizer adaptation time Line input impedance (RTIP and ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 22 Microprocessor Input Timing Diagram SCLK CDH SDI R/W CONTROL BYTE Figure 23 Microprocessor Output Timing Diagram CS SCLK tCDV High Z SDO ® ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 24 CMI Encoded Zero per G.703 and STS-3 V 0.60 (Note 1) 0.55 0.50 0.45 0.40 Nominal 0.05 zero level –0.05 (Note 2) –0.40 –0.45 –0.50 –0.55 –0.60 ® Cortina ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 25 CMI Encoded One per G.703 and STS-3 V 0.60 (Note 1) 0.55 0.50 0.45 0.40 (Note 4) Nominal 0.05 zero level – 0.05 (Note 2) – 0.40 – 0.45 ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 26 Jitter Tolerance (template Values from Table 34) 100 10 1 0.1 10Hz 1Hz Table 35 Jitter Generation 1 Signal f1 OC3 12 kHz 500 Hz STM1 65 kHz 1. ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 27 Jitter Generation Measurement Filter Characteristics Figure 28 Typical Coax Jitter Transfer -10 -20 -30 -40 1 Measured with the device in remote loopback. Data reflects ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 Figure 29 Typical Fiber Jitter Transfer -10 -20 -30 -40 1 Measured with the device in remote loopback. Data reflects total jitter in both Tx and Rx ...
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LXT6155 Transceiver Datasheet 249612, Revision 7.0 14 Feburary 2007 7.0 Mechanical Specifications Figure 30 LXT6155 Transceiver LE Package Specification Table 37 LXT6155 Transceiver LE Package Specification (64-Pin Low-Profile Quad Flat Pack) Inches Dim Min A — A1 ...
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