AM27C512-120JC Spansion Inc., AM27C512-120JC Datasheet - Page 5

• Manufacturer Part Number: AM27C512-120JC
• Manufacturer: Spansion Inc.

Specifications of AM27C512-120JC

• Organization: 64Kx8
• Interface Type: Parallel
• In System Programmable: External
• Access Time (max): 120ns
• Package Type: PLCC
• Reprogramming Technique: OTP
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 25mA
• Pin Count: 32
• Mounting: Surface Mount
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed con-
tents, the device must be exposed to an ultraviolet light
source. A dosage of 15 W seconds/cm
completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp—wavelength
of 2537 Å—with intensity of 12,000 µW/cm
minutes. The device should be directly under and
about one inch from the source, and all filters should be
removed from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro-
cedure.
The device enters the programming mode when 12.75
V 0.25 V is applied to the OE#/V
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data pins.
The flowchart in the Programming section of the
EPROM Products Data Book (Section 5, Figure 5-1)
shows AMD’s Flashrite algorithm. The Flashrite algo-
rithm reduces programming time by using a 100 µs pro-
gramming pulse and by giving each address only as
many pulses to reliably program the data. After each
pulse is applied to a given address, the data in that ad-
dress is verified. If the data does not verify, additional
pulses are given until it verifies or the maximum pulses
allowed is reached. This process is repeated while se-
quencing through each address of the device. This part
of the algorithm is done at V
each EPROM bit is programmed to a sufficiently high
threshold voltage. After the final address is completed,
the entire EPROM memory is verified at V
5.25 V.
Please refer to Section 5 of the EPROM Products Data
Book for additional programming information and spec-
ifications.
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#, all like in-
puts of the devices may be common. A TTL low-level
program pulse applied to one device’s CE# input with
V
IL
.
CC
= 6.25 V to assure that
PP
pin, and CE# is at
2
is required to
2
CC
for 15 to 20
= V
PP
Am27C512
=
OE#/V
lar device. A high-level CE# input inhibits the other de-
vices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE#/V
at V
Autoselect Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25 C
ambient temperature range that is required when pro-
gramming the device.
To activate this mode, the programming equipment
must force V
may then be sequenced from the device outputs by
toggling address line A0 from V
ing the address from 00h to 01h). All other address
lines must be held at V
Byte 0 (A0 = V
and Byte 1 (A0 = V
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable
(CE#) and Output Enable (OE#/V
low. CE# controls the power to the device and is typi-
cally used to select the device. OE#/V
device to output data, independent of device selection.
Addresses must be stable for at least t
to the Switching Waveforms section for the timing dia-
gram.
Standby Mode
The device enters the CMOS standby mode when CE#
is at V
100 µA. The device enters the TTL-standby mode
when CE# is at V
to 1.0 mA. When in either standby mode, the device
places its outputs in a high-impedance state, indepen-
dent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function provides:
n Low memory power dissipation, and
n Assurance that output bus contention will not occur.
IL
, and V
CC
PP
= 12.75 V
0.3 V. Maximum V
PP
H
on address line A9. Two identifier bytes
IL
between 12.5 V and 13.0 V.
) represents the manufacturer code,
IH
IH
. Maximum V
), the device identifier code. Both
0.25 V, will program that particu-
IL
during the autoselect mode.
CC
IL
CC
to V
current is reduced to
PP
current is reduced
IH
) must be driven
PP
ACC
(that is, chang-
enables the
PP
–t
OE
and CE#
. Refer
5 C
5