SLCF2GM2PUI STEC, SLCF2GM2PUI Datasheet - Page 10

• Manufacturer Part Number: SLCF2GM2PUI
• Manufacturer: STEC
• Type: CompactFlashr

Specifications of SLCF2GM2PUI

• Density: 2GByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: Not Required
• Pin Count: 50
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.97/4.5V
• Operating Supply Voltage (max): 3.63/5.5V
• Programmable: Yes
• Lead Free Status / Rohs Status: Compliant

SLCFxxx(G)M2PU(I)
Datasheet
WP
(PC Card Memory Mode)
Write Protect
-IOIS16
(PC Card I/O Mode)
-IOCS16
(True IDE Mode)
-INPACK
(PC Card Memory Mode
except UDMA protocol
active)
-DMARQ
(PC Card Memory Mode:
UDMA protocol active)
-INPACK
(PC Card I/O Mode except
UDMA protocol active)
Input Acknowledge
-DMARQ
(PC Card I/O Mode: UDMA
protocol active)
DMARQ
(True IDE Mode)
BVD1
(PC Card Memory Mode)
-STSCHG
(PC Card I/O Mode)
Status Changed
-PDIAG
(True IDE Mode)
O
O
I/O
24
43
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61000-05610-108, April 2009
The CF Card does not have a write protect switch; therefore,
this signal is held low after the completion of the reset
initialization sequence.
A low signal indicates that a 16 bit or odd byte only operation
can be performed at the addressed port.
In True IDE Mode this output signal is asserted low when this
device is expecting a word data transfer cycle.
This signal is not used in this mode.
This signal is a DMA Request that is used for DMA data
transfers between host and device. It shall be asserted by the
device when it is ready to transfer data to or from the host.
For Multiword DMA transfers, the direction of data transfer is
controlled by -IORD and -IOWR. This signal is used in a
handshake manner with (-)DMACK, i.e., the device shall wait
until the host asserts (-)DMACK before negating (-)DMARQ,
and re-asserting (-)DMARQ if there is more data to transfer.
In PCMCIA I/O Mode, the -DMARQ shall be ignored by the
host while the host is performing an I/O Read cycle to the
device. The host shall not initiate an I/O Read cycle while -
DMARQ is asserted by the device.
In True IDE Mode, DMARQ shall not be driven when the
device is not selected in the Drive-Head register.
While a DMA operation is in progress, -CS0 (-CE1)and -CS1
(-CE2) shall be held negated and the width of the transfers
shall be 16 bits.
If there is no hardware support for True IDE DMA mode in
the host, this output signal is not used and should not be
connected at the host. In this case, the BIOS must report that
DMA mode is not supported by the host so that device
drivers will not attempt DMA mode operation.
A host that does not support DMA mode and implements
both PC Card and True IDE modes of operation need not
alter the PC Card mode connections while in True IDE mode
as long as this does not prevent proper operation in any
mode.
The Input Acknowledge signal is asserted by the CF Card
when it is selected and responding to an I/O read cycle at the
address that is on the bus. The host uses this signal to
control the enable of any input data buffers between the CF
Card and the host’s CPU.
Same as (-)DMARQ above.
Same as (-)DMARQ above.
This signal is asserted high as since a battery is not used
with this product.
Asserted low to alert host to changes in RDY/-BSY, Write Protect
states. Use is controlled by Configuration and Status Register.
In True IDE Mode, this input/output signal is the Pass
Diagnostic signal in the Master/Slave handshake protocol.
CompactFlash Card
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