MPC190VFB Freescale Semiconductor, MPC190VFB Datasheet

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MPC190VFB

Manufacturer Part Number
MPC190VFB
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC190VFB

Mounting
Surface Mount
Lead Free Status / Rohs Status
Not Compliant
Advance Information
MPC190CE/D
Rev. 3, 7/2003
MPC190
Security Processor
Chip Errata
This document details all known silicon errata for the MPC190 and its derivatives. Table 1
provides a revision history for this document.
Table 2 provides a revision history of the MPC190 silicon.
Rev. No.
0
1
2
3
Freescale Semiconductor, Inc.
For More Information On This Product,
Initial release.
Added Errata 8.
Added Errata 9–11.
Added Errata 12. Updated template.
Silicon Revision
XPC190VFB
XPC190VFA
PPC190VF
Go to: www.freescale.com
Table 1. Document Revision History
Table 2. Silicon Revision History
Applicable Errata/Enhancements
Substantive Changes
3–6, 8, 12
3–6, 9–12
1–8, 12

Related parts for MPC190VFB

MPC190VFB Summary of contents

Page 1

... Freescale Semiconductor, Inc. Advance Information MPC190CE/D Rev. 3, 7/2003 MPC190 Security Processor Chip Errata This document details all known silicon errata for the MPC190 and its derivatives. Table 1 provides a revision history for this document. Rev. No Table 2 provides a revision history of the MPC190 silicon. ...

Page 2

... Freescale Semiconductor, Inc. Errata No. 1: REQ64 Internal Delay Detailed Description and Projected Impact: The PPC190 does not sample the PCI REQ64 signal at the correct time when operating at 66 MHz. For a 64-bit PCI bus (any clock speed), the system board asserts the REQ64 during RESET to all 64-bit slots. The PCI device samples REQ64 on the negation of reset to determine the width of the slot that it is inserted into ( bits) ...

Page 3

... Freescale Semiconductor, Inc. Errata No. 2: RNG Static Mode Operation Detailed Description and Projected Impact: The PPC190 allows for two modes of execution unit operation—static and dynamic. In static mode, a particular execution unit is assigned to a crypto-channel. Static descriptors are used to perform multiple operations with that execution unit without changing keys or context, thus, reducing context switching overhead ...

Page 4

... Freescale Semiconductor, Inc. Errata No. 3: PCI Configuration Header—Base Address Register 0[3] Detailed Description and Projected Impact: Bit 3 (taccess) is also known as the prefetchable attribute bit. This bit is hardwired to 1, indicating that the PPC190 is prefetchable. Although it is memory mapped, most of the PPC190 is not ‘well-behaved’ memory, and should not be prefetched to avoid destructive reads ...

Page 5

... Freescale Semiconductor, Inc. Errata No. 4: AFEU Context-Dump Issue Detailed Description and Projected Impact: Using a context-dump static descriptor on the AFEU leaves undefined state. If the AFEU is not reset (because static mode) and is not loaded with new context (which is the intended behavior), then the it is left expecting new context, and will not start up correctly when data is pushed into the FIFO. This issue is observed when the current drivers try to break a > ...

Page 6

... Freescale Semiconductor, Inc. Errata No. 5: AFEU Context Loading and Unloading Erroneously Loaded into MDEU Input FIFO When Snooping Detailed Description and Projected Impact: The MDEU works on the same data as AFEU/DEU by ‘snooping.’ The channel tells the controller to tell the MDEU to pick up the same data written to/read from the encryption EU FIFO. In normal operation, after the first ARC-4 key permute, AFEU context is preserved from packet to packet by unloading and reloading the S-box contents ...

Page 7

... Freescale Semiconductor, Inc. Errata No. 6: 2Key 3DES Parity Error Detailed Description and Projected Impact: The DEU supports single DES and triple DES using either 2Key (112-bit key) or 3Key (68-bit key) modes. The type of triple DES keying is determined by the number of bytes a key specifies in the descriptor. ...

Page 8

... Freescale Semiconductor, Inc. Errata No. 7: MDEU Autopad Detailed Description and Projected Impact: Autopadding for MD-5 and SHA-1 does not function reliably. Performing the suggested work around will lower system performance slightly. Work Around: All packets must be padded at the application level. All descriptors with autopadding must not be used. ...

Page 9

... MPC190 must only perform single reads. This can be accomplished by setting the latency timer to 0x00 setting the single target read bit in the MPC190 controller. Projected Solution: A more robust buffering scheme has been determined, and will be implemented on the MPC190VFB. MOTOROLA MPC190 Security Processor Chip Errata For More Information On This Product, Go to: www ...

Page 10

... Errata No. 9: Enhancement: PKEU Mode Register Change Detailed Description and Projected Impact: The PKEUs in the MPC190VFB has been upgraded to reduce the number of descriptors needed to perform sign and verify operations. Specifically, a PKEU mode has been added which consolidates three lower level 2 operations (R mod N, mod mult, and mod exp) into a single routine called ‘ ...

Page 11

... Freescale Semiconductor, Inc. Errata No. 10: Enhancement: Interrupt Mask Register (IMR) Change Detailed Description and Projected Impact: The default setting of all XPC190 interrupt sources is ‘unmasked.’ To assist the user in avoiding multiple unintended interrupts prior to proper configuration of the 190, a new bit (bit 63, GIE) has been added to the controller’ ...

Page 12

... Freescale Semiconductor, Inc. Errata No. 11: Enhancement: Master Control Register (MCR) Change Detailed Description and Projected Impact: To assist the user (and device driver) in determining which revision of XPC190 silicon is available to the system, a revision ID field has been added to the 190 master control register. This bit (32) will reset the PPC190VF and XPC190VFA, and will reset the XPC190VFB ...

Page 13

... Freescale Semiconductor, Inc. Errata No. 12: PKEU Address Error Detailed Description and Projected Impact: Not all addresses in the PKEU map to functional registers or memories. The PKEU address error is meant to advise the user that a read or write has occurred to a hole in the PKEU address map, however, the PKEU signals address error (via the PKEU interrupt status register) for all accesses to the PKEU, regardless of whether the address falls into a hole ...

Page 14

... Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK 14 MPC190 Security Processor Chip Errata For More Information On This Product, Go to: www.freescale.com MOTOROLA ...

Page 15

... Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA MPC190 Security Processor Chip Errata For More Information On This Product, Go to: www.freescale.com 15 ...

Page 16

... HOME PAGE: www.motorola.com/semiconductors Freescale Semiconductor, Inc. Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...

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