IS42S32400E-7BI-TR ISSI, Integrated Silicon Solution Inc, IS42S32400E-7BI-TR Datasheet

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... IS42S32400E IS45S32400E 128Mb SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.3V • LVTTL interface • Programmable burst length – ( full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 4096 refresh cycles every 16ms (A2 grade (Commercial, Industrial, A1 grade) • ...

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... IS42S32400E, IS45S32400E DEVICE OVERVIEW The 128Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V V and 3.3V V memory systems containing 134,217,728 ddq bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 33,554,432-bit bank is orga- nized as 4,096 rows by 256 columns by 32 bits. The 128Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode. All signals are registered on the positive edge of the clock signal, CLK. ...

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... IS42S32400E, IS45S32400E PIN CONFIGURATIONS 86 pin TSOP - Type II for x32 V DD DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM0 WE CAS RAS CS A11 BA0 BA1 A10 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 V DD PIN DESCRIPTIONS A0-A11 Row Address Input A0-A7 Column Address Input ...

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... IS42S32400E, IS45S32400E PIN CONFIGURATION PACKAGE CODE BALL TF-BGA (Top View) (8. 13.00 mm Body, 0.8 mm Ball Pitch PIN DESCRIPTIONS A0-A11 Row Address Input A0-A7 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command Column Address Strobe Command CAS DQ26 DQ24 VSS VDD DQ28 VDDQ VSSQ VDDQ VSSQ ...

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... IS42S32400E, IS45S32400E PIN FUNCTIONS Symbol Type A0-A11 Input Pin BA0, BA1 Input Pin CAS Input Pin CKE Input Pin CLK Input Pin CS Input Pin D QM0-DQM3 Input Pin DQ0-DQ31 I nput/Output Pin RAS Input Pin WE Input Pin V P ower Supply Pin ddq V P ower Supply Pin ower Supply Pin ssq V P ower Supply Pin ss Integrated Silicon Solution, Inc. - www.issi.com Rev. E ...

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... IS42S32400E, IS45S32400E GENERAL DESCRIPTION READ The READ command selects the bank from BA0, BA1 inputs and starts a burst read access to an active row. Inputs A0-A7 provides the starting column location. When A10 is HIGH, this command functions as an AUTO PRECHARGE command. When the auto precharge is selected, the row being accessed will be precharged at the end of the READ burst. The row will remain open for subsequent accesses when AUTO PRECHARGE is not selected. DQ’s read data is subject to the logic level on the DQM inputs two clocks earlier. When a given DQM signal was registered HIGH, the corresponding DQ’s will be High-Z two clocks later. DQ’ ...

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... IS42S32400E, IS45S32400E COMMAND TRUTH TABLE CKE Function n – 1 Device deselect (DESL operation (NOP) H Burst stop (BST) H Read H Read with auto precharge H Write H Write with auto precharge H Bank activate (ACT) H Precharge select bank (PRE) H Precharge all banks (PALL) H CBR Auto-Refresh (REF) H Self-Refresh (SELF) H Mode register set (MRS) H Note: H Valid Data DQM TRUTH TABLE Function Data write / output enable Data mask / output disable ...

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... IS42S32400E, IS45S32400E CKE TRUTH TABLE Current State /Function Activating Clock suspend mode entry Any Clock suspend mode Clock suspend mode exit Auto refresh command Idle (REF) Self refresh entry Idle (SELF) Power down entry Idle Self refresh exit Power down exit Note: H Valid Data CKE n – RAS CAS × × × × × × × × × × × ...

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... IS42S32400E, IS45S32400E FUNCTIONAL TRUTH TABLE Current State CS RAS CAS WE Idle Row Active Read Write Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/10 Address Command X X DESL H X NOP L X BST H BA, CA, A10 READ/READA L A, CA, A10 WRIT/ WRITA ...

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... IS42S32400E, IS45S32400E FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Read with auto H × × Precharging Write with Auto H × × Precharge Precharging H × × Row Activating H × × Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Address Command × × DESL H x NOP L × BST H BA, CA, A10 ...

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... IS42S32400E, IS45S32400E FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Write Recovering H × × Write Recovering H × × with Auto Precharge Refresh H × × Mode Register H × × Accessing L L × Note: H Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Notes: 1. All entries assume that CKE is active (CKEn-1=CKEn=H both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will be disabled. 3. Illegal to bank in specified states ...

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... IS42S32400E, IS45S32400E CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK ( would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t rc Idle After t rc Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle Illegal Illegal Exit clock suspend next cycle Maintain clock suspend Power-Down (P.D.) INVALID, CLK ( would exit P.D. EXIT P.D. --> Idle (2) Maintain power down mode Both Banks Idle ...

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... IS42S32400E, IS45S32400E STATE DIAGRAM Mode Register Set BST Write CKE WRITE WRITE SUSPEND CKE CKE WRITEA WRITEA SUSPEND CKE Precharge POWER ON Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/10 SELF SELF exit MRS REF IDLE CKE CKE ACT CKE Row Active CKE ...

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... IS42S32400E, IS45S32400E ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage in V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current cs T operating Temperature opr T Storage Temperature stg Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All voltages are referenced to Vss. ...

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... IS42S32400E, IS45S32400E DC ELECTRICAL CHARACTERISTICS 1 Symbol Parameter i Operating Current (1) dd1 i Precharge Standby Current dd2p (In Power-Down Mode) i Precharge Standby Current dd2ps (In Power-Down Mode) i Precharge Standby Current dd2n (2) (In Non Power-Down Mode) I Precharge Standby Current dd2ns (In Non Power-Down Mode) i Active Standby Current (2) dd3n (In Non Power-Down Mode) I Active Standby Current dd3ns (In Non Power-Down Mode) I Active Standby Current dd3p (Power-Down Mode) I Active Standby Current dd3ps (Power-Down Mode) i Operating Current dd4 i Auto-Refresh Current dd5 i Self-Refresh Current dd6 Notes specified at the output open condition. ...

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... IS42S32400E, IS45S32400E AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time ck3 t ck2 t Access Time From CLK ac3 t ac2 t CLK HIGH Level Width ch t CLK LOW Level Width cl t Output Data Hold Time oh3 t oh2 t Output LOW Impedance Time lz t Output HIGH Impedance Time CAS Latency = 3 hz3 t hz2 t Input Data Setup Time ( Input Data Hold Time ( Address Setup Time ( Address Hold Time ( CKE Setup Time (2) cks t CKE Hold Time (2) ckh t Command Setup Time (CS, RAS, CAS, WE, DQM) cms t Command Hold Time (CS, RAS, CAS, WE, DQM) ...

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... IS42S32400E, IS45S32400E OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t CAS Latency cac t Active Command To Read/Write Command Delay Time rcd t RAS Latency ( rac rcd cac t Command Period (REF to REF / ACT to ACT Command Period (ACT to PRE) ras t Command Period (PRE to ACT Command Period (ACT[0] to ACT [1]) rrd t Column Command Delay Time ccd (READ, READA, WRIT, WRITA) ...

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... IS42S32400E, IS45S32400E AC TEST CONDITIONS Input Load t CH 3.0V 1.4V CLK CMS CMH 3.0V INPUT 1. OUTPUT 1.4V AC TEST CONDITIONS Parameter AC Input Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Measurement Reference Level 18 Output Load 1.4V 1. 50Ω Output 50 pF Rating 1.4V 1.4V Integrated Silicon Solution, Inc. - www.issi.com 50Ω Rev. E ...

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... IS42S32400E, IS45S32400E FUNCTIONAL DESCRIPTION The 128Mb SDRAMs are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 33,554,432-bit banks is organized as 4,096 rows by 256 columns by 32 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an AC- TIVE command which is then followed by a READ or W RITE command ...

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... IS42S32400E, IS45S32400E INITIALIzE AND LOAD MODE REGISTER CLK CKS CKH CKE CMS CMH CMS CMH COMMAND NOP PRECHARGE DQM0-DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS Power-up: V Precharge CC and CLK stable all banks T = 100µs Min. Notes: 1 ...

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... IS42S32400E, IS45S32400E AUTO-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z Notes: 1. CAS latency = 2, 3 Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/ Auto NOP ...

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... IS42S32400E, IS45S32400E SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Precharge all active banks refresh mode Note: 1. Self-Refresh Mode is not supported for A2 grade with CKS ≥ t RAS Auto ...

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... IS42S32400E, IS45S32400E REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. MODE REGISTER DEFINITION BA1 BA0 A11 A10 A9 (1) Reserved Write Burst Mode ...

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... IS42S32400E, IS45S32400E BURST LENGTH Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length deter- mines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected ...

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... IS42S32400E, IS45S32400E CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge The DQs will start driving as a result of the clock edge one cycle earlier ( 1), and provided that the relevant access times are met, the data will be valid by clock edge For example, assuming that the clock ...

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... IS42S32400E, IS45S32400E CHIP OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the t specification. Minimum t should be divided by rcd rcd the clock period and rounded up to the next whole number ...

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... IS42S32400E, IS45S32400E READS READ bursts are initiated with a READ command, as shown in the READ COMMAND diagram. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the fol- lowing illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge ...

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... IS42S32400E, IS45S32400E diagram for each possible CAS latency; data element either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until t is met. Note that part of the row precharge time is rp hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge ...

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... IS42S32400E, IS45S32400E RW1 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 2 RW2 - READ to WRITE T0 CLK DQM COMMAND READ BANK, ADDRESS COL n DQ Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/ NOP NOP NOP NOP n+1 D n+2 OUT OUT ...

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... IS42S32400E, IS45S32400E CONSECUTIVE READ BURSTS T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP READ BANK, COL n+1 D OUT OUT NOP NOP READ BANK, COL n+1 OUT OUT ...

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... IS42S32400E, IS45S32400E RANDOM READ ACCESSES T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/ READ READ READ BANK, BANK, BANK, COL b COL m COL OUT OUT CAS Latency - 2 T1 ...

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... IS42S32400E, IS45S32400E READ BURST TERMINATION T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP NOP NOP TERMINATE n+1 D OUT OUT BURST NOP NOP TERMINATE n+1 OUT OUT T5 T6 NOP ...

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... IS42S32400E, IS45S32400E ALTERNATING BANK READ ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN A10 ROW BA0, BA1 BANK BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = Full Page 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E READ - DQM OPERATION CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD Notes: 1) CAS latency = 2, Burst Length = 4 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP PRECHARGE BANK (a or all n+1 D n+2 D OUT OUT OUT NOP NOP NOP PRECHARGE ...

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... IS42S32400E, IS45S32400E WRITES WRITE bursts are initiated with a WRITE command, as shown in WRITE Command diagram. WRITE COMMAND CLK HIGH CKE CS RAS CAS WE A0-A7 COLUMN ADDRESS A8, A9, A11 AUTO PRECHARGE A10 NO PRECHARGE BA0, BA1 BANK ADDRESS The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. ...

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... IS42S32400E, IS45S32400E WRITE BURST COMMAND ADDRESS WRITE TO WRITE RANDOM WRITE CYCLES COMMAND ADDRESS CLK WRITE NOP NOP BANK, COL n CLK COMMAND WRITE NOP BANK, ADDRESS COL n DON'T CARE CLK WRITE WRITE WRITE BANK, BANK, BANK, COL n COL b COL NOP DON'T CARE ...

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... IS42S32400E, IS45S32400E WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WP1 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/ NOP READ NOP BANK, COL b D n+1 IN CAS Latency - NOP NOP NOP PRECHARGE BANK ...

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... IS42S32400E, IS45S32400E WP2 - WRITE to PRECHARGE T0 CLK DQM COMMAND WRITE BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS NOP NOP NOP PRECHARGE BANK (a or all) t DPL D n CLK BURST WRITE TERMINATE COMMAND BANK, (ADDRESS) COL (DATA) IN DON'T CARE NOP ACTIVE BANK a, ROW ...

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... IS42S32400E, IS45S32400E WRITE - FULL PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = Full Page 2) x32: A8, A9, A11 = "Don't Care" Integrated Silicon Solution, Inc. - www.issi.com Rev ...

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... IS42S32400E, IS45S32400E WRITE - DQM OPERATION T0 t CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD Notes: 1) Burst Length = 4 2) x32: A8, A9, A11 = "Don't Care" WRITE NOP NOP t t CMS ...

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... IS42S32400E, IS45S32400E ALTERNATING BANK WRITE ACCESSES CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK 0 BANK BANK 0 RCD t RRD t - BANK 0 RAS t - BANK 0 RC Notes: 1) Burst Length = 4 2) x32: A8, A9, A11 = " ...

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... IS42S32400E, IS45S32400E CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time Clock Suspend During WRITE Burst T0 CLK CKE INTERNAL CLOCK COMMAND NOP ADDRESS DQ Clock Suspend During READ Burst ...

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... IS42S32400E, IS45S32400E CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM0 - DQM3 A0-A9, A11 COLUMN m ( A10 BA0, BA1 BANK DQ Notes: 1) CAS latency = 3, Burst Length = 2, Auto Precharge is disabled. 2) x32: A8, A9, A11 = "Don't Care" Integrated Silicon Solution, Inc. - www.issi.com Rev ...

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... IS42S32400E, IS45S32400E PRECHARGE The PRECHARGE command (see figure) is used to deac- tivate the open row in a particular bank or the open row in all banks bank(s) will be available for a subsequent row access some specified time (t ) after the PRECHARGE rp command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged the idle state and must be activated prior to any READ or WRITE commands being issued to that bank ...

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... IS42S32400E, IS45S32400E POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0 - DQM3 A0-A9, A11 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks power-down mode Note: x32: A8, A9, A11 = " ...

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... IS42S32400E, IS45S32400E BURST READ/SINGLE WRITE The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI ...

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... IS42S32400E, IS45S32400E WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing (CAS latency) later. The PRECHARGE to bank n will begin after t is met, where t begins when the READ to bank m is dpl registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. ...

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... IS42S32400E, IS45S32400E SINGLE READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E READ WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E SINGLE READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 1 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E READ WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) CAS latency = 2, Burst Length = 4 2) x32: A8, A9, A11 = " ...

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... IS42S32400E, IS45S32400E SINGLE WRITE WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9, A11 ROW A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x32: A8, A9, A11 = "Don't Care" must not be violated. ...

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... IS42S32400E, IS45S32400E SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW DISABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 1 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E WRITE - WITHOUT AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP DQM0 - DQM3 A0-A9, A11 ROW A10 ROW t t DISABLE AUTO PRECHARGE AS AH BA0, BA1 BANK DQ t RCD t RAS t RC Notes: 1) Burst Length = 4 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E WRITE - WITH AUTO PRECHARGE CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP WRITE t CMS DQM0 - DQM3 A0-A9, A11 ROW COLUMN ENABLE AUTO PRECHARGE A10 ROW BA0, BA1 BANK RCD t RAS t RC Notes: 1) Burst Length = 4 2) x32: A8, A9, A11 = "Don't Care" ...

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... IS42S32400E, IS45S32400E ORDERING INFORMATION - V Commercial Range: 0°C to +70°C Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S32400E-6TL 166 MHz 6 IS42S32400E-6B 166 MHz 6 IS42S32400E-6BL 143 MHz 7 IS42S32400E-7TL 143 MHz 7 IS42S32400E-7BL 133 MHz 7.5 IS42S32400E-75ETL Industrial Range: -40°C to +85°C Frequency Speed (ns) Order Part No. 166 MHz 6 IS42S32400E-6TLI 166 MHz 6 IS42S32400E-6BLI 143 MHz 7 IS42S32400E-7TLI ...

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... IS42S32400E, IS45S32400E Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/10 59 ...

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... IS42S32400E, IS45S32400E 60 D1 Integrated Silicon Solution, Inc. - www.issi.com Rev. E 10/28/10 ...