SMFV008 Samsung Semiconductor, SMFV008 Datasheet
SMFV008
Specifications of SMFV008
Related parts for SMFV008
SMFV008 Summary of contents
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... SMFV008 Document Title Bit SmartMedia Revision History Revision No. History 0.0 Data Sheet, 1997 1.0 Data Sheet, 1998 1. Changed t BERS 2. Changed Valid Block Number : 1004(Min.) 1.1 Data Sheet 1998 1.2 Data Sheet 1999 1. Added CE don’ t care mode during the data-loading and reading The attached datasheets are prepared and approved by SAMSUNG Electronics ...
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... ECC. The SMFV008 is an optimum solution for large nonvolatile stor- age applications such as solid state file storage, digital voice recorder, digital still camera and other portable applications requiring non-volatility ...
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... SMFV008 Figure 1. FUNCTIONAL BLOCK DIAGRAM Command Figure 2. ARRAY ORGANIZATION 16K Row 1st half Page Register (=1024 Block) (=256 Bytes) 512B column Page Register 512 Byte I/O 0 1st Cycle A 0 2nd Cycle A 9 3rd Cycle A 17 NOTE : Column Address : Starting Address of the Register. ...
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... The memory array consists of 1024 separately erasable 8K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the SMFV008. The SMFV008 has addresses multiplexed into 8 I/O s. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design ...
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... SMFV008 PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register ...
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... SMFV008 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Temperature Under Bias Storage Temperature Short Circuit Output Current NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet ...
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... NOTE : 1. The SMFV008 may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles, the minimum number of valid blocks are guaran- teed though its initial number could be reduced ...
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... SMFV008 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...
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... SMFV008 SmartMedia Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block( called as the invalid block informa- tion ...
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... SMFV008 SmartMedia Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung minimizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. Refer to the qualification report for the actual data ...
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... SMFV008 SmartMedia Technical Notes (Continued) Erase Flow Chart Start Write 60H Write Block Address Write D0H Write 70H SR R Erase Error SR Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. Block Replacement Buffer ...
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... Pointer Operation of SMFV008 The SMFV008 has three read modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations ...
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... SMFV008 System Interface Using CE don’ t -care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... SMFV008 * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLS CLH ALS ALH Command CLS WH t ALS SmartMedia ALH ...
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... SMFV008 * Input Data Latch Cycle CLE CE t ALS ALE WE I Sequential Out Cycle after Read DIN 0 DIN 1 (CLE=L, WE=H, ALE= REH t t REA REA Dout Dout NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ...
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... SMFV008 * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE I/O ~ 00h or 01h Column Address R/B t CLS t CLS t CLH WHR 70H AR2 Dout N Dout N Page(Row) Address Busy 16 SmartMedia t CSTO t CHZ t RSTO RHZ Status Output t RC Dout N+3 Dout N+2 ...
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... SMFV008 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE 00h or 01h I Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE A 50H I R/B M Address AR2 tRR Dout Page(Row) Address Busy :Valid Address :Don t care SmartMedia t CHZ t RC Dout N+1 Dout N+2 ...
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... SMFV008 SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00H I R/B M PAGE PROGRAM OPERATION CLE ALE RE 80H I Sequential Data Column Input Command Address R/B Dout Dout N+1 Busy N Output t WC Din Din N 528 Byte Data Page(Row) Sequential Input Address 18 SmartMedia Dout Dout ...
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... SMFV008 BLOCK ERASE OPERATION CLE ALE RE 60H I Block Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/O ~ 90H 0 7 Read ID Command (ERASE ONE BLOCK DOH 17 22 Erase Command t READID 00H 19 SmartMedia t BERS 70H Busy ...
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... SMFV008 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read oper- ation ...
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... SMFV008 Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50H Start Add.(3Cycle) I & Don't Care) Figure 5. Sequential Row Read1 Operation R/B I 00H Start Add.(3Cycle) 01H & 1st half array Data Field 1st half array 2nd half array Data Field Spare Field ...
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... SMFV008 Figure 6. Sequential Row Read2 Operation R/B 50H Start Add.(3Cycle) I Don't Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten ...
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... SMFV008 BLOCK ERASE The Erase operation is done on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. ...
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... SMFV008 READ ID The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of 00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (E6H) respectively. The command regis- ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence. ...
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... SMFV008 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... SMFV008 DIMENSIONS 22 PAD SOLID STATE FLOPPY DISK CARD (3.3V) SOLID STATE PRODUCT OUTLINE 5.0 0.2 Index Label Area 10.0 0.2 Write Protect Area 0.5mm Chamfer 4.2(Min) (3.3V Card) 8.650 7.900 6.500 0.000 37.0 0.1 33.0 0.2 45.1 0.1 1.5 0.1 2.70 ...