54ACT299FMQB. National Semiconductor, 54ACT299FMQB. Datasheet - Page 2

• Manufacturer Part Number: 54ACT299FMQB.
• Manufacturer: National Semiconductor
• Type: Not Requiredr

Specifications of 54ACT299FMQB.

• Technology: CMOS
• Number Of Elements: 1
• Number Of Bits: 8
• Logic Family: ACT
• Logical Function: Shift Register
• Operating Supply Voltage (typ): 5V
• Output Type: 3-State
• Propagation Delay Time: 18ns
• Operating Temp Range: -55C to 125C
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / Rohs Status: Not Compliant

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Connection Diagrams
Functional Description
The ’AC/’ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform syn-
chronous shift left, shift right, parallel load and hold opera-
tions. The type of operation is determined by S
shown in the Truth Table. All flip-flop outputs are brought out
through TRI-STATE buffers to separate I/O pins that also
serve as data inputs in the parallel load mode. Q
also brought out on other pins for expansion in serial shifting
of longer words.
A LOW signal on MR overrides the Select and CP inputs and
resets the flip-flops. All other state changes are initiated by
the rising edge of the clock. Inputs can change when the
clock is in either state provided only that the recommended
setup and hold times, relative to the rising edge of CP, are
observed.
A HIGH signal on either OE
buffers and puts the I/O pins in the high impedance state. In
this condition the shift, hold, load and reset operations can
still occur. The TRI-STATE buffers are also disabled by HIGH
signals on both S
operation.
CP
DS
DS
S
MR
OE
I/O
Q
0
0
, S
, Q
Pin Names
0
7
0
1
–I/O
, OE
1
7
7
2
0
and S
Clock Pulse Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Mode Select Inputs
Asynchronous Master Reset
TRI-STATE Output Enable Inputs
Parallel Data Inputs or
TRI-STATE Parallel Outputs
Serial Outputs
1
1
in preparation for a parallel load
or OE
2
disables the TRI-STATE
Description
(Continued)
0
0
and S
and Q
1
7
, as
are
2
Truth Table
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
MR
H
H
H
H
L
= LOW-to-HIGH Transition
S
X
H
H
L
L
Inputs
1
S
H
H
X
L
L
0
CP
N
N
N
X
X
Asynchronous Reset;
Q
Parallel Load; I/O
Shift Right; DS
Q
Shift Left, DS
Q
Hold
0
0
7
–Q
7
Q
Q
= LOW
1
6
Response
, etc.
, etc.
7
0
n
Q
Q
7
,
0
Q
,
n