AD8116-EB Analog Devices Inc, AD8116-EB Datasheet - Page 8

• Manufacturer Part Number: AD8116-EB
• Manufacturer: Analog Devices Inc

Specifications of AD8116-EB

• Lead Free Status / Rohs Status: Not Compliant

EVAL-AD8116EB
Optimized for video applications, all signal inputs and outputs
are terminated with 75 W resistors. Figure 7 shows a cross
section of one of the input or output tracks along with the
arrangement of the PCB layers. It should be noted that unused
regions of the four layers are filled up with ground planes. As a
result, the input and output traces, in addition to having con-
trolled impedances, are well shielded.
The board has 32 BNC type connectors: 16 inputs and 16 outputs.
The connectors are arranged in two crescents around the device.
As can be seen from Figure 4, this results in all 16 input signal
traces and all 16 output signal traces having the same length.
This is useful in tests such as All-Hostile Crosstalk where the
phase relationship and delay between signals needs to be main-
tained from input to output.
The four power supply pins AVCC, DVCC, AVEE, and DVEE
should be connected to good quality, low noise, ± 5 V supplies.
Where the same ± 5 V power supplies are used for analog and
digital, separate cables should be run for the power supply to the
evaluation board’s analog and digital power supply pins.
Figure 7. Cross Section of Input and Output Traces
a = 0.008"
(0.2mm)
w = 0.008"
(0.2mm)
(0.714mm)
c = 0.028"
t = 0.00135" (0.0343mm)
b = 0.0132"
d = 0.0132"
(0.335mm)
(0.335mm)
TOP LAYER
SIGNAL LAYER
POWER LAYER
BOTTOM LAYER
–8–
As can be seen in Figure 8, there is extensive power supply
decoupling on the evaluation board. Figure 8 shows the location
of all the decoupling capacitors relative to the AD8116’s pins.
Four large 10 mF capacitors are located near the evaluation
board’s power supply connection terminals. These decouple
the AVCC, DVCC, AVEE, and DVEE supplies. Because it is
required that the voltage difference between DGND and
AGND never exceed 0.7 V, these grounds are connected by
two antiparallel diodes. On the output side of the device (Pin 65
to Pin 96), the 16 output pins are interleaved with the AVCC
and AVEE power supply pins. Each of these pins is locally
decoupled with a 0.01 mF capacitor. These pins are also decoupled
in groups of four with 0.1 mF capacitors. Due to space constraints,
the power supply Pins 34 (DVCC) and 42 (DVEE) are neither
connected nor decoupled. These pins are, however, internally
connected to DVCC and DVEE (Pins 127 and 119).
As a general rule, each power supply pin (or group of adjacent
power supply pins) should be locally decoupled with a 0.01 mF
capacitor. If there is a space constraint, it is more important to
decouple analog power supply pins before digital power supply
pins. A 0.1 mF capacitor, located reasonably close to the pins,
can be used to decouple a number of power supply pins. Finally,
a 10 mF capacitor should be used to decouple power supplies as
they come onto the board.
REV. 0