PEB20571FV31XT Lantiq, PEB20571FV31XT Datasheet - Page 149

• Manufacturer Part Number: PEB20571FV31XT
• Manufacturer: Lantiq

Specifications of PEB20571FV31XT

• Lead Free Status / Rohs Status: Compliant

Data Transfer from the µP to the OAK
• The µP reads the busy bit and checks whether the Mailbox is available (MBUSY=’0’)
• The µP writes to the Data registers MDTn (optional)
• The µP writes to the µP Command register (MCMD), this write must be performed and
• An OAK interrupt (INT2) is activated due to the write to the Command register
• The OAK INT2 routine reads MCMD and performs the command (the read of the
• When finished, the INT2 routine resets MBUSY for enabling the µP to send the next
Note: The µP may perform consecutive writes to the µP Mailbox, and the user must
4.9.3
The OAK Mailbox includes:
• Eight 16-bit data registers (ODTx)
• A 16-bit general register (OGEN)
• An 8-bit command register (OCMD)
• A 1-bit busy register (OBUSY)
Registers ODTx, OGEN and OCMD may be written by the OAK and read by the µP. The
OBUSY bit may be written by the P and read by the OAK. In addition, the P can read
this bit (because the P could poll this bit).
A write of the OAK to register OCMD of the OAK mailbox generates an interrupt to the
µP. Thus the OAK firmware provides all mailbox data prior to writing to register OCMD.
The OBUSY- bit which can be read by the OAK, is set automatically after a write of the
OAK to register OCMD and is reset by a direct µP write to it (when the µP has finished
reading the OAK Mailbox contents).
Note: The Opcodes indications are defined in DELIC-LC/-PB Software User’s Manual.
Data Sheet
sets automatically the µP Mailbox busy bit (MBUSY).
(MCMD).
command register resets the INT2 activation signal).
command.
guarantee that the data has been transferred to the OAK correctly (the busy bit has
been reset) before writing new data to the µP Mailbox.
OAK Mailbox
132
Functional Description
PEB 20570
PEB 20571
2003-07-31