AD9779ABSVZ Analog Devices Inc, AD9779ABSVZ Datasheet
AD9779ABSVZ
Specifications of AD9779ABSVZ
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AD9779ABSVZ Summary of contents
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FEATURES Low power: 1 GSPS, 600 mW @ 500 MSPS, full operating conditions Single carrier W-CDMA ACLR = 80 dBc @ 80 MHz IF Analog output: adjustable 8 31.7 mA Ω to ...
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AD9776A/AD9778A/AD9779A TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Typical Signal Chain ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 DC Specifications ......................................................................... 5 Digital ...
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REVISION HISTORY 9/08—Rev Rev. B Changed Serial Peripheral Interface (SPI) to 3-Wire Interface Throughout ................................................................................... 1 Change to Features Section .............................................................. 1 Change to Applications Section ...................................................... 1 Changes to Integral Nonlinearity (INL) Parameter, Table 1 ....... 5 ...
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AD9776A/AD9778A/AD9779A DELAY SYNC_O LINE SYNC_I DELAY DATACLK LINE DATA ASSEMBLER I P1D[15:0] LATCH 2× Q LATCH 2× P2D[15:0] PERIPHERAL AD9779A FUNCTIONAL BLOCK DIAGRAM CLOCK GENERATION/DISTRIBUTION 2× 2× × /8 DAC ... 7 2× ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN ...
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AD9776A/AD9778A/AD9779A DIGITAL SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. LVDS driver and receiver are compliant to the IEEE-1596 reduced range link, ...
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DIGITAL INPUT DATA TIMING SPECIFICATIONS All modes, −40°C to +85°C. Table 3. Parameter Conditions 1 INPUT DATA Setup Time Input data to DATACLK Hold Time Input data to DATACLK Setup Time Input data to REFCLK Hold Time Input data to ...
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AD9776A/AD9778A/AD9779A AC SPECIFICATIONS AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1 MIN MAX otherwise noted. Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR 100 MSPS, f ...
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ABSOLUTE MAXIMUM RATINGS Table 5. Parameter With Respect To AVDD33, DVDD33 AGND, DGND, CGND DVDD18, CVDD18 AGND, DGND, CGND AGND DGND, CGND DGND AGND, CGND CGND AGND, DGND I120, VREF, IPTAT AGND OUT1_P, OUT1_N, AGND OUT2_P, OUT2_N, AUX1_P, AUX1_N, AUX2_P, ...
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AD9776A/AD9778A/AD9779A PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND ...
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Pin No. Mnemonic Description 33 DVDD18 1.8 V Digital Supply Connect Connect Connect. 37 DATACLK Data Clock Output. 38 DVDD33 3.3 V Digital Supply. 39 TXENABLE/ Transmit Enable. In single port ...
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AD9776A/AD9778A/AD9779A 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 ...
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Pin No. Mnemonic Description 37 DATACLK Data Clock Output. 38 DVDD33 3.3 V Digital Supply. 39 TXENABLE/ Transmit Enable. In single port mode, this IQSELECT pin also functions as IQSELECT. 40 P2D13 Port 2, Data Input D13 (MSB). 41 P2D12 ...
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AD9776A/AD9778A/AD9779A 100 CVDD18 1 PIN 1 CVDD18 2 CGND 3 CGND 4 REFCLK+ 5 REFCLK– 6 ...
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Pin No. Mnemonic Description 37 DATACLK Data Clock Output. 38 DVDD33 3.3 V Digital Supply. 39 TXENABLE/ Transmit Enable. In single port mode, this IQSELECT pin also functions as IQSELECT. 40 P2D15 Port 2, Data Input D15 (MSB). 41 P2D14 ...
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AD9776A/AD9778A/AD9779A TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 –3 –4 –5 –6 0 10k 20k 30k 40k CODE Figure 6. AD9779A Typical INL 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 10k 20k 30k 40k CODE ...
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DATA 200MSPS DATA DATA (MHz) OUT Figure 12. AD9779A Out-of-Band SFDR vs. f 2× Interpolation 100 150MSPS DATA 70 ...
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AD9776A/AD9778A/AD9779A 100 f = 160MSPS DATA 250MSPS 80 DATA (MHz) OUT Figure 18. AD9779A Third-Order IMD vs. f 1× Interpolation 100 f = 160MSPS DATA ...
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OUT Figure 24. AD9779A IMD Performance vs. f Digital Full-Scale Input Over Output Frequency, 4× Interpolation, ...
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AD9776A/AD9778A/AD9779A –150 –154 f = 200MSPS DAC –158 f DAC –162 f = 800MSPS DAC –166 –170 (MHz) OUT Figure 30. AD9779A Noise Spectral Density vs Over Output Frequency with a Single-Tone Input ...
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CODE Figure 36. AD9778A Typical INL 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 10k 12k CODE Figure 37. AD9778A Typical DNL 100 ...
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AD9776A/AD9778A/AD9779A –150 –154 f = 200MSPS DAC –158 f DAC –162 f = 800MSPS DAC –166 –170 (MHz) OUT Figure 42. AD9778A Noise Spectral Density vs. f for Eight-Tone Input with 500 kHz Spacing, f ...
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FIRST ADJACENT CHANNEL –70 THIRD ADJACENT CHANNEL –75 –80 SECOND ADJACENT CHANNEL –85 – 100 125 150 175 F (MHz) OUT Figure 48. AD9776A ACLR vs. f OUT f = 122.88 MSPS, 4× ...
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AD9776A/AD9778A/AD9779A TERMINOLOGY Integral Nonlinearity (INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure ...
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THEORY OF OPERATION The AD9776A/AD9778A/AD9779A have many features that make them highly suited for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband ...
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AD9776A/AD9778A/AD9779A 3-WIRE INTERFACE The 3-wire port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard micro- controllers and microprocessors. The port is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR ...
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SERIAL INTERFACE PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and controls the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the ...
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AD9776A/AD9778A/AD9779A 3-WIRE INTERFACE REGISTER MAP Note that all unused register bits should be kept at the device default values. Table 13. Address Register Name Hex Decimal Bit 7 Comm 0x00 00 SDIO bidirectional Digital 0x01 01 Interpolation Factor[1:0] Control 0x02 ...
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Table 14. 3-Wire Interface Register Description Register Register Name Address Bits Comm 0x00 7 0x00 6 0x00 5 0x00 4 0x00 3 0x00 1 Digital Control 0x01 7:6 0x01 5:2 0x01 1 0x01 0 0x02 7 0x02 6 0x02 5 ...
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AD9776A/AD9778A/AD9779A Register Register Name Address Bits Sync Control 0x03 7 0x03 6 0x03 5:4 0x03 3:0 0x04 7:4 0x04 3:1 0x04 0 0x05 7:4 0x05 3:1 0x05 0 0x06 7:4 0x06 3:0 0x07 7 0x07 6 0x07 5 0x07 4:0 ...
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Register Register Name Address Bits PLL Control 0x08 7:2 0x08 1:0 0x09 7 0x09 6:5 0x09 4:3 0x09 2:0 Misc. Control 0x0A 7:5 0x0A 4:0 I DAC Control 0x0C 1:0 0x0B 7:0 0x0C 7 0x0C 6 Aux DAC1 Control 0x0E ...
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AD9776A/AD9778A/AD9779A Register Register Name Address Bits AUX DAC2 Control 0x12 1:0 0x11 7:0 0x12 7 0x12 6 0x12 5 0x13 to 0x18 Interrupt 0x19 7 0x19 6 0x19 4 0x19 3 0x19 2 0x19 0 Version 0x1F 7:0 Parameter Function ...
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INTERPOLATION FILTER ARCHITECTURE The AD9776A/AD9778A/AD9779A can provide up to 8× inter- polation, or the interpolation filters can be entirely disabled important to note that the input signal should be backed off by approximately 0.01 dB from full scale ...
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AD9776A/AD9778A/AD9779A 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –4 –3 –2 – (× Input Data Rate) OUT Figure 58. 4× Interpolation, Low-Pass Response to ±4× Input Data Rate (Dotted Lines Indicate 1 dB ...
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Input Data Rate) OUT Figure 64. Interpolation/Modulation Combination of − –10 –20 –30 –40 –50 –60 –70 –80 ...
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AD9776A/AD9778A/AD9779A Table 19. Interpolation Filter Modes, (Register 0x01, Bits[5:2]) Interpolation Filter Modulation Factor[7:6] Mode[5:2] 8 0x00 8 0x01 8 0x02 8 0x03 8 0x04 8 0x05 8 0x06 8 0x07 8 0x08 8 0x09 8 0x0A 8 0x0B 8 0x0C ...
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INTERPOLATION FILTER BANDWIDTH LIMITS The AD9776A/AD9778A/AD9779A use a novel interpolation filter architecture that allows DAC IF frequencies to be gener- ated anywhere in the spectrum. Figure 68 shows the traditional choice of DAC IF output bandwidth placement. Note that there ...
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AD9776A/AD9778A/AD9779A As shown in Table 20, the mixing functions of most of the modes result in cross-coupling of samples between the I and Q channels. The I and Q channels only operate independently with the f /2 mode. This means ...
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SOURCING THE DAC SAMPLE CLOCK The AD9776A/AD9778A/AD9779A offer two modes of sourcing the DAC sample clock (DACCLK). The first mode employs an on-chip clock multiplier that accepts a reference clock operating at the lower input frequency, most commonly the data ...
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AD9776A/AD9778A/AD9779A Table 23. Typical VCO Frequency Range vs. PLL Band Select Value PLL Lock Ranges Over Temperature, −40°C to +85°C VCO Frequency Range (MHz) PLL Band Select f LOW 111111 (63) Auto mode 111110 (62) 1975 111101 (61) 1956 111100 ...
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Configuring PLL Band Select with Temperature Sensing The following procedure outlines a method for setting the PLL band select value for a device operating at a particular temperature that holds for a change in ambient temperature over the total −40°C ...
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AD9776A/AD9778A/AD9779A DRIVING THE REFCLK INPUT The REFCLK input requires a low jitter differential drive signal. The signal level can range from 400 mV p-p differential to 1.6 V p-p differential centered about a 400 mV input common- mode voltage. Looking ...
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FULL-SCALE CURRENT GENERATION INTERNAL REFERENCE Full-scale current on the I DAC and Q DAC can be set from 8. 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external ...
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AD9776A/AD9778A/AD9779A GAIN AND OFFSET CORRECTION Analog quadrature modulators make it very easy to realize single sideband radios. However, there are several nonideal aspects of quadrature modulator performance. Among these analog degradations are • Gain mismatch: The gain in the real ...
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AUX1_P 500Ω AD9779A 250Ω LPI 390nH 93 OUT1_P RBIP 82pF 50Ω 39pF C1I C2I RBIN 92 50Ω OUT1_N LNI 82pF 390nH 250Ω C3I 89 AUX1_N 500Ω 87 AUX2_N 500Ω LNQ 250Ω 390nH 84 OUT2_N RBQN 82pF 50Ω C1Q 39pF ...
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AD9776A/AD9778A/AD9779A INPUT DATA PORTS The AD9776A/AD9778A/AD9779A can operate in two data input modes: dual port mode and single port mode. For the default dual port mode (single port bit = 0), each DAC receives data from a dedicated input port. ...
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The DATACLKDIV only affects the DATACLK output frequency, not the frequency of the data sampling clock. To maintain an f frequency that samples the input data that remains DATACLK consistent with the expected data rate, DATACLKDIV should be set to ...
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AD9776A/AD9778A/AD9779A OPTIMIZING THE DATA INPUT TIMING The AD9776A/AD9778A/AD9779A have on-chip circuitry that enables the user to optimize the input data timing by adjusting the relationship between the DATACLK output and DCLK_SMP (the internal clock that samples the input data). This ...
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DEVICE SYNCHRONIZATION System demands can impose two different requirements for synchronization. Some systems require multiple DACs to be synchronized to each other. This is the case when supporting transmit diversity or beam forming, where multiple antennas are used to transmit ...
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AD9776A/AD9778A/AD9779A SYNCHRONIZING DEVICES TO A SYSTEM CLOCK The AD9776A/AD9778A/AD9779A offer a pulse mode synchro- nization scheme (see Figure 89) to align the DAC outputs of multiple devices within a system to the same DACCLK edge. The internal clocks are synchronized ...
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POWER DISSIPATION Figure 91 to Figure 99 show the power dissipation of the 1.8 V and 3.3 V digital and clock supplies in single DAC mode and dual DAC mode. In addition to this, the power dissipation/current of the 3.3 ...
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AD9776A/AD9778A/AD9779A 0.125 8× INTERPOLATION, f /8, DAC f /4, DAC f /2, DAC NO MODULATION 0.100 4× INTERPOLATION 0.075 0.050 0.025 100 125 150 f (MSPS) DATA Figure 97. Power Dissipation, Clock 1.8 V Supply, ...
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EVALUATION BOARD OVERVIEW EVALUATION BOARD OPERATION The AD9776A/AD9778A/AD9779A evaluation board is provided to help users quickly become familiar with the operation of the device and to evaluate the device performance. To operate the evaluation board, the user needs a PC, ...
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AD9776A/AD9778A/AD9779A The evaluation board comes with software that allows the user to program the on-chip configuration registers. Via the 3-wire interface port, the devices can be programmed into any of its various operating modes. The default software window is shown ...
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... AD9776ABSVZ −40°C to +85°C 1 AD9776ABSVZRL −40°C to +85°C 1 AD9778ABSVZ −40°C to +85°C 1 AD9778ABSVZRL −40°C to +85°C 1 AD9779ABSVZ −40°C to +85°C 1 AD9779ABSVZRL −40°C to +85°C 1 AD9776A-EBZ 1 AD9778A-EBZ 1 AD9779A-EBZ RoHS Compliant Part. 14.00 BSC PIN 1 TOP VIEW ...
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AD9776A/AD9778A/AD9779A NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06452-0-9/08(B) Rev Page ...