LS029B4DN01 Sharp Electronics, LS029B4DN01 Datasheet - Page 17

• Manufacturer Part Number: LS029B4DN01
• Manufacturer: Sharp Electronics

Specifications of LS029B4DN01

• Lead Free Status / Rohs Status: Compliant

8-2) Input Signal Timing Chart
8-2-1 Data update mode (1 line)
SCS
SI
SCLK
Updates data of only one specified line. (M0=”H”、M2＝”L”)
M0: Mode flag. Set for “H”. Data update mode (Memory internal data update)
M1: Frame inversion flag.
M2: All clear flag.
DUMMY DATA: Dummy data. It can be “H” or “L” (“L” is recommended.)
tsSCS
* Data write period
* Data transfer period
tsSI
Mode select period
M0
Data is being stored in 1
Data written in 1
(3ck)
M1
thSI
When “H”, outputs VCOM=”H”, and when “L”, outputs VCOM=”L”.
When EXTMODE=”H”, it can be “H” or “L”.
450
451
452
453
454
455
456
GL AG0 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8
1
2
3
4
5
6
7
8
:
When “L”, display mode (maintain memory internal data).
M2
Refer to 8-2-4) All Clear Mode to execute clear.
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
:
AG0 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
:
twSCLKL
Gate line address setup
st
latch is being transferred (written) to pixel internal memory circuit.
Gate line address select period
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
:
st
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
:
latch block of binary driver on panel.
twSCLKH
(9ck)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
twSCSH
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
:
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
:
DUMMY DATA(don't care)
Dummy period
(12ck)
D1
D2
D3
D4
D237 D238 D239 D240
Date write period
(240ck)
SPEC No.
LCY-12T09X02A
Date transfer period
(24ck)
DUMMY DATA(don't care)
MODEL No.
LS029B4DN01
thSCS
PAGE
twSCSL
15