LM97593VH/HALF National Semiconductor, LM97593VH/HALF Datasheet - Page 42

• Manufacturer Part Number: LM97593VH/HALF
• Manufacturer: National Semiconductor

Specifications of LM97593VH/HALF

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F
magnitude is at least 25dB below the dc value from F
9F
circuit is about 10dB below the dc this means that the ripple
in the detected level is about 0.7dB or less for input frequen-
cies
AGC_COMB_ORD register to either 1 or 2 will narrow the
power detector’s bandwidth as shown in Figure 39.
The “FIXED TO FLOAT CONVERTER” takes the fixed point
9-bit output from the CIC filter and converts it to a “floating
point” number. This conversion is done so that the 32 values
in the RAM can be uniformly assigned (dB scale) to detected
power levels (54 dB range). This provides a resolution of
1.7dB between detected power levels. The truth table for this
converter is given in Table 4. The upper three bits of the out-
put represent the exponent (e) and the lower 2 are the man-
tissa (m). The exponent is determined by the position of the
leading ‘1’ out of the CIC filter. An output of ‘001XX’ corre-
sponds to a leading ‘1’ in bit 2 (LSB is bit 0). The exponent
increases by one each time the leading ‘1’ advances in bit
position. The mantissa bits are the two bits that follow the
leading ‘1’. If we define E as the decimal value of the exponent
bits and M as the decimal value of the mantissa bits, the out-
put of the CIC filter, POUT, corresponding to a given “FIXED
TO FLOAT CONVERTER” output is:
The max() and min() operators account for row 1 of Table 4
which is a special case because M=P
ciates each address of the RAM with a CIC filter output.
As shown in Figure 40, the 32X8 RAM look-up table imple-
ments the functions of log converter, reference subtraction,
error amplifier, and deadband. The user must build each of
these functions by constructing a set of 8-bit, 2’s complement
numbers to be loaded into the RAM. Each of these functions
and how to construct them are discussed in the following
paragraphs.
A log conversion is done in order to keep the loop gain inde-
pendent of operating point. To see why this is beneficial, the
control gain of the DVGA computed without log conversion is:
where G is the decimal equivalent of GAIN and G
for the DVGA gain in excess of unity. This equation assumes
CK
CK
/8, where F
/10. Because the 2
TABLE 4. Fixed to Float Converter Truth Table
between
128-255
256-511
INPUT
64-127
16-31
32-63
8-15
CK
0-3
4-7
is the clock frequency, and the response
F
CK
/20
nd
harmonic from the absolute value
to
OUTPUT (eeemm)
19F
000XX
001XX
010XX
011XX
100XX
101XX
110XX
111XX
CK
OUT
/20.
. Equation 5 asso-
Setting
o
(Eq. 10)
accounts
CK
(Eq. 9)
/10 to
the
42
that the DVGA gain control polarity is positive as is the case
for the CLC5526. The gain around the entire loop must be
negative. Observe in Equation 6 that the control gain is de-
pendent on operating point G. If we instead compute the
control gain with log conversion then:
which is no longer operating-point dependent. The log func-
tion is constructed by computing the CIC filter output associ-
ated with each address (Equation 5) and converting these to
dB. Full scale (dc signal) is 20log(511)=54dB.
The reference subtraction is constructed by subtracting the
desired loop servo point (in dB) from the table values com-
puted in the previous paragraph. For example, if it is desired
that the DVGA servo the ADC input level (sinusoidal signal)
to -6dBFS, the number to subtract from the data is:
The table data will then cross through zero at the address
corresponding to this reference level. A deadband wider than
6dB should then be constructed symmetrically about this
point. This prevents the loop from hunting due to the 6dB gain
steps of the DVGA. Any deadband in excess of 6dB appears
as hysteresis in the servo point of the loop as illustrated in
Figure 37. The deadband is constructed by loading zeros into
those addresses on either side of the one which corresponds
to the reference level.
The last function of the RAM table is that of error amplification.
All the operations preceding this one gave a table slope
S
time constant of the loop given by:
The term G
The design equations are obtained by solving Equation 13 for
G
register value that determines the number of bits to shift the
output of the RAM down by. This allows some of the loop gain
to be moved out of the RAM so that the full output range of
the table is utilized but not exceeded. The valid range for
AGC_LOOP_GAIN is from 0 to 3 which corresponds to a 0 to
3 bit shift to the left.
An example set of numbers to implement a loop having a ref-
erence of 6dB below full scale, a deadband of 8dB, and a loop
gain of 0.108 is:
RAM
L
and Equation 14 for S
= 1. This must now be adjusted in order to control the
-102 -102 -88 -80 -75 -70 -66
-63 -61 -56 -53 -50
-47 -42 -39 -36 -33 -29 -25
-22 -19 -15 -11 -0
0 0 0 0 0 13 17 20
L
in this equation is the loop gain:
RAM
. AGC_LOOP_GAIN is a control
(Eq. 11)
(Eq. 12)
(Eq. 13)
(Eq. 14)