LTC4259ACGW#TRMPBF Linear Technology, LTC4259ACGW#TRMPBF Datasheet - Page 26

• Manufacturer Part Number: LTC4259ACGW#TRMPBF
• Manufacturer: Linear Technology

Specifications of LTC4259ACGW#TRMPBF

• Linear Misc Type: Negative Voltage
• Family Name: LTC4259A
• Operating Supply Voltage (min): -48V
• Operating Supply Voltage (max): -57V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Lead Free Status / Rohs Status: Compliant

APPLICATIO S I FOR ATIO
LTC4259A
clock pulse. The slave must pull down the SDA line during
the Acknowledge clock pulse so that it remains a stable
LOW during the HIGH period of this clock pulse. When the
master is reading from a slave device, it is the master’s
responsibility to acknowledge receipt of the data byte in
the bit that follows unless the transaction is complete. In
that case the master will decline to acknowledge and issue
the STOP condition to terminate the communication.
Write Byte Protocol
The master initiates communication to the LTC4259A with
a START condition and a 7-bit bus address followed by the
Write Bit (Wr) = 0. If the LTC4259A recognizes its own
address, it acknowledges and the master delivers the com-
mand byte, signifying to which internal LTC4259A register
the master wishes to write. The LTC4259A acknowledges
and latches the lower five bits of the command byte into its
Register Address register. Only the lower five bits of the
command byte are checked by the LTC4259A; the upper
three bits are ignored. The master then delivers the data
byte. The LTC4259A acknowledges once more and latches
the data into the appropriate control register. Finally, the
master terminates the communication with a STOP condi-
tion. Upon reception of the STOP condition, the Register
Address register is cleared (see Figure 7).
Read Byte Protocol
The master initiates communication from the LTC4259A
with a START condition and the same 7-bit bus address
followed by the Write Bit (Wr) = 0. If the LTC4259A
recognizes its own address, it acknowledges and the
master delivers the command byte, signifying which
internal LTC4259A register it wishes to read from. The
LTC4259A acknowledges and latches the lower five bits
of the command byte into its Register Address register. At
this time the master sends a REPEATED START condition
and the same 7-bit bus address followed by the Read Bit
(Rd) = 1. The LTC4259A acknowledges and sends the
contents of the requested register. Finally, the master
declines to acknowledge and terminates communication
with a STOP condition. Upon reception of the STOP
condition, the Register Address register is cleared (see
Figure 8).
26
U
U
W
U
Receive Byte Protocol
Since the LTC4259A clears the Register Address register
on each STOP condition, the interrupt register (register 0)
may be read with the Receive Byte Protocol as well as with
the Read Byte Protocol. In this protocol, the master
initiates communication with the LTC4259A with a START
condition and a 7-bit bus address followed by the Read Bit
(Rd) = 1. The LTC4259A acknowledges and sends the
contents of the interrupt register. The master then de-
clines to acknowledge and terminates communication
with a STOP condition (see Figure 9).
Alert Response Address and the INT Pin
In a system where several LTC4259As share a common INT
line, the master can use the Alert Response Address (ARA)
to determine which LTC4259A initiated the interrupt.
The master initiates the ARA procedure with a START
condition and the 7-bit ARA bus address (0001100)b
followed by the Read Bit (Rd) = 1. If an LTC4259A is
asserting the INT pin, it acknowledges and sends its 7-bit
bus address (010A
While it is sending its address, it monitors the SDAIN pin
to see if another device is sending an address at the same
time using standard I
is sending a 1 and reads a 0 on the SDAIN pin on the rising
edge of SCL, it assumes another device with a lower
address is sending and the LTC4259A immediately aborts
its transfer and waits for the next ARA cycle to try again.
If transfer is successfully completed, the LTC4259A will
stop pulling down the INT pin. When the INT pin is released
in this way or if a 1 is written into the Clear Interrupt pin bit
(bit 6 of register 1Ah), the condition causing the LTC4259A
to pull the INT pin down must be removed before the
LTC4259A will be able to pull INT down again. This can be
done by reading and clearing the event registers or by
writing a 1 into the Clear All Interrupts bit (bit 7 of register
1Ah). The state of the INT pin can only change between I
transactions, so an interrupt is cleared or new interrupts
are generated after a transaction completes and before
new I
of the alert response address can be used instead of the
INT pin if desired. If any device acknowledges the alert
response address, then the INT line, if connected, would
have been low.
2
C bus communication commences. Periodic polling
3
A
2
2
C bus arbitration. If the LTC4259A
A
1
A
0
)b and a 1 (see Figure 10).
4259afb
2
C