K4T1G164QF-BCE6 Samsung Semiconductor, K4T1G164QF-BCE6 Datasheet - Page 41

• Manufacturer Part Number: K4T1G164QF-BCE6
• Manufacturer: Samsung Semiconductor

Specifications of K4T1G164QF-BCE6

• Lead Free Status / Rohs Status: Compliant

K4T1G044QF
K4T1G084QF
K4T1G164QF
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance
11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be
12. tQH = tHP - tQHS, where :
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output slew rate
14. tDAL = WR + RU{ tRP[ns] / tCK[ns] }, where RU stands for round up.
15. The clock frequency is allowed to change during self refresh mode or precharge power-down mode.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the ODT resis-
17. ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance. Both are mea-
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST),
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due
tHP = minimum half clock period for any given cycle and is defined by clock HIGH or clock LOW (tCH, tCL).
tQHS accounts for:
Example: For DDR533 at tCK = 3.75ns with WR programmed to 4 clocks.
(bus turnaround) will degrade accordingly.
greater than the minimum specification limits for tCL and tCH). For example, tCL and tCH are = 50% of the period, less the half period jitter ( tJIT(HP))
of the clock source, and less the half period jitter due to crosstalk ( tJIT(crosstalk)) into the clock traces.
mismatch between DQS/ DQS and associated DQ in any given cycle.
tCK refers to the application clock period.
tance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns (= 2 x 5 ns) after
the clock edge that registered a first ODT HIGH if tCK = 5 ns. For DDR2-667/800, tAOND is 2 clock cycles after the clock edge that registered a first
ODT HIGH counting the actual input clock edges.
sured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is 12.5 ns (= 2.5 x 5 ns) after the clock edge that regis-
tered a first ODT LOW if tCK = 5 ns. For DDR2-667/800, if tCK(avg) = 3 ns is assumed, tAOFD is 1.5 ns (= 0.5 x 3 ns) after the second trailing clock
edge counting from the clock edge that registered a first ODT LOW and by counting the actual input clock edges.
specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) . Figure 19 shows a method to calculate the point when device is no
longer driving (tHZ), or beginsdriving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as
long as the calculation is consistent. tLZ(DQ) refers to tLZ of the DQS and tLZ(DQS) refers to tLZ of the (U/L/R)DQS and (U/L/R)DQS each treated as
single-ended signal.
or begins driving (tRPRE). Figure 19 shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving
(tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consis-
tent.
WR refers to the tWR parameter stored in the MRS. For tRP, if the result of the division is not already an integer, round up to the next highest integer.
tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
to data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers.
tRPST end point
tHZ,tRPST end point = 2*T1-T2
tHZ
Figure 19. Method for calculating transitions and endpoints
T1
T2
V
V
V
V
datasheet
OH
OH
OL
OL
+ 2x mV
+ x mV
+ x mV
+ 2x mV
- 41 -
V
V
V
V
TT
TT
TT
TT
tLZ,tRPRE begin point = 2*T1-T2
+ 2x mV
+ x mV
- x mV
- 2x mV
T1
T2
tLZ
DDR2 SDRAM
Rev. 1.11