LM4934WL National Semiconductor, LM4934WL Datasheet - Page 26

• Manufacturer Part Number: LM4934WL
• Manufacturer: National Semiconductor

Specifications of LM4934WL

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Interface Control Register
FIR Compensation Filter
Configuration Registers
These registers are used to configure the DAC’s FIR com-
pensation filter. Three 16 bit coefficients are required and
must be programmed via the I2C/SPI Interface in bytes as
follows:
COMP_COEFF (10h → 15h) (Set = logic 1, Clear = logic 0)
NOTES:
The filter must be phase linear to ensure the data keeps the correct stereo imaging so the second half of the FIR filter must be the reverse of the 1st half.
If the CUST_COMP option in register 0Eh is not set the FIR filter will use its default values for a linear response from the DAC
into the analog mixer, these values are:
If using 96 or 192kHz data then the custom compensation
may be required to obtain flat frequency responses above
24kHz. The total power of any custom filter must not exceed
Address
10h
11h
12h
13h
14h
15h
DAC_OSR
01, 10, 11
00
COMP_COEFF0_MSB
COMP_COEFF1_MSB
COMP_COEFF2_MSB
COMP_COEFF0_LSB
COMP_COEFF1_LSB
COMP_COEFF2_LSB
Register
(Continued)
C0, C4
112
Left Justified Mode Timing
68
26
that of the above examples or the filters within the DAC will
clip. The coefficient must be programmed in 2’s complement.
Bits [15:8] of the 2nd and 4th FIR tap (C1 and C3)
Bits [15:8] of the 1st and 5th FIR tap (C0 and C4)
Bits [7:0] of the 2nd and 4th FIR tap (C1 and C3)
Bits [7:0] of the 1st and 5th FIR tap (C0 and C4)
Bits [15:8] of the 3rd FIR tap (C2)
Bits [7:0] of the 3rd FIR tap (C2)
C1, C3
–412
–580
Description
20166955
28526
27551
C2
201669B0