UTOPIA16EVK/NOPB National Semiconductor, UTOPIA16EVK/NOPB Datasheet
UTOPIA16EVK/NOPB
Specifications of UTOPIA16EVK/NOPB
UTOPIA16EVK/NOPB Summary of contents
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... Order Number Package Information DS92UT16TUF 196 LBGA package, 15x15x1.37 mm, 1.0 mm ball pitch © 2004 National Semiconductor Corporation — Two independent LVDS receiver serial ports for optional 1:1 protection — Main and redundant LVDS transmit ports — Loop timing capability enables LVDS recovered clock to internally drive LVDS transmit clock — ...
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Block Diagram 5.0 Application Overview www.national.com FIGURE 1. DS92UT16 Block Diagram 2 20031601 ...
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Application Overview The UTOPIA interface [1. See Section 21.0 References established standard for connecting Physical Layer de- vices to ATM Layer devices. However, when the ATM Layer device and the Physical Layer device(s) are on separate cards ...
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Functional Description Note: The full connections for a single sub-port are shown in Figure 4. FIGURE 3. Extended UTOPIA Level 2 for 248 PHY Ports www.national.com (Continued) 4 20031603 ...
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Functional Description FIGURE 4. Detailed Connection of One Sub-Port for Extended UTOPIA Level 2 For the purposes of queueing, the 248 PHY ports are con- figured as sub-ports of the standard 31 ports so each port/ queue has 8 ...
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Functional Description Note: Default MTB queue thresholds must be changed to use this configuration. See Section 9.2 MULTIPLE BRIDGE MTB CONFIGURATION Parity generation and checking is available in all modes. To support systems where routing tags and/or padding are ...
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Functional Description 6.3.1 Cell Rate Decoupling In the down-bridge direction, the TCS Assembler inserts idle cells when no valid traffic cells are available from the FIFO for onward transmission. In the up-bridge direction, the TCS Disassembler rejects all received ...
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Functional Description During normal operation in the up-bridge direction, the de- vice monitors the HEC bytes for errors, with an option to reject cells containing errored HEC’s. A performance metric on the number of errored cells detected is maintained. ...
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Functional Description TABLE 4. F Channel Byte Usage Within the Frame TC0 TC1 TC2 Flow Control 3 Flow Control 1 Flow Control 3 Flow Control 2 Flow Control 0 Flow Control 2 TC7 TC8 TC9 Flow Control 3 Flow ...
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Functional Description Buffer with a corresponding Rx Buffer Full Flag. All bytes of the buffers are software read/write accessible. Tx Buffer Ready is read only. At the ECC transmit side, the reset state sets the Tx Buffer Ready flag ...
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Functional Description tial outputs with independent TRI-STATE The same data is transmitted over both pairs of transmit pins. The two serial receive interfaces are completely sepa- rate and independent and are denoted Port A and Port B. Only one ...
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Functional Description LineLB_LVDS Physical loopback at the LVDS interface. Loop entering LVDS traffic back out of the device. LocalLB_LVDS Physical loopback at the LVDS interface. Loop exiting LVDS traffic back into the device. Up2Down_ATM ATM loopback. Route defined cell ...
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Signal Description Signal Name LVDS INTERFACE LVDS_ADout[+,−] A Serial data differential outputs. LVDS_BDout[+,−] B Serial data differential outputs. LVDS_ADenb Serial transmit data A output enable. LVDS_BDenb Serial transmit data B output enable. LVDS_Synch External control to transmit SYNCH patterns ...
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Signal Description Note 2: These pins are Outputs in ATM Layer mode and Inputs PHY Layer mode. Note 3: These pins are only used in PHY layer mode, Extended 248 PHY mode. In Normal 31 PHY mode or ATM ...
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UTOPIA Interface Operation FIGURE 8. Basic UTOPIA Level 2 UMODE Configuration 8.1.1 ATM Polling When configured as an ATM Layer device, the DS92UT16 polls the connected PHY ports using the MPhy address busses U_TxAddr and U_RxAddr. Only those ports ...
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UTOPIA Interface Operation FIGURE 9. Extended UTOPIA Level 2 UMODE Configuration The main difference is that in ATM mode the CLAV pins are inputs and the MPhy Address and ENB pins are outputs, whereas in PHY mode the CLAV ...
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UTOPIA Interface Operation (Continued) port address of 0 and a sub-port address of 7 means that the destination PHY is MPhy address 0 attached to U_TxENB[7] and U_TxCLAV[7]. The cell is then transmitted to that PHY. Receive Path Example: ...
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UTOPIA Interface Operation (Continued) nected Port are defined by the UCSPL register bit location in the UCSPL register is set, then that sub-port is connected. In Figure 11, the registers are set as follows: UCPL3 = UCPL2 ...
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MTB Queue Configuration (Continued further recommended that any queue that is not being used is set with a threshold of zero. When a queue has reached its programmed threshold the device flow control mechanism will prevent the ...
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Configuration and Traffic Inhibit Operation (Continued) The device can now be reconfigured safely. When configu- ration is completed, then the CTI bit can be cleared by the processor and normal operation resumed. Note that the CTI bit is set ...
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Cell/Frame Delineation and Descrambler Operation Note that depending on the length of the TC and the length of the TC Header it may be necessary to word slip after a predefined number of HEC calculations in order to obtain ...
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Cell/Frame Delineation and Descrambler Operation lock, then the transmitted RDSLL = 1. At the far end device, this is stored as RARDSLL or RBRDSLL, depending on which port it is connected to. When this bit is set for the ...
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Cell/Frame Delineation and Descrambler Operation or start-up until it receives the cleared RDSLL bit in the Remote Alarm and Signaling byte. After TC delineation oc- curs at the receive end, the DS92UT16 will count correct scrambler sequence predictions until ...
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LVDS Interface Operation (Continued) instance, if LVDS_TxClk = 50 MHz, the payload data rate 800 Mbps. LVDS_TxClk is provided by the data source and must be in the range of 30 MHz to 52 ...
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LVDS Interface Operation (Continued) at the far end will be corrupted. This is because the scram- bler lock works on a frame-by-frame basis and each frame is 56 transport containers long. For this reason switching to or from Loop ...
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Performance Monitoring Performance Counter RAHECC2–RAHECC0 (Section 18.27 RECEIVE PORT A HEC COUNT — 0x2E to 0x30 RAHECC2 to RAHECC0) RABIPC2–RABIPC0 (Section 18.29 RECEIVE PORT A BIP COUNT — 0x34 to 0x36 RABIPC2 to RABIPC0) RABEC2–RABEC0 (Section 18.39 RECEIVE PORT ...
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Performance Monitoring Alarms ETXBR (Section 18.10 ECC ECC transmit buffer ready for new message. TRANSMIT BUFFER AND RECEIVE LVDS ALARMS — 0x0A ETXRXA) RALLC (Section 18.23 RECEIVE Receive Port A. Link Label Change of value. PORT A LOCAL ALARMS ...
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Performance Monitoring Alarms RBLCS (Section 18.42 RECEIVE PORT B LOCAL ALARMS — 0x62 RBLA) RBLDSLL (Section 18.42 RECEIVE PORT B LOCAL ALARMS — 0x62 RBLA) RBLTCLL (Section 18.42 RECEIVE PORT B LOCAL ALARMS — 0x62 RBLA) RBLFLL (Section 18.42 ...
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Performance Monitoring Alarms MTBHOVA (Section 18.72 MTB Hard overflow. The MTB queue has overflowed (up-bridge). UTOPIA AND ATM ALARMS — 0xE1 UAA) 15.0 Loopback Operation To assist in diagnostic testing, the DS92UT16 provides both physical interface loopbacks and ATM ...
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Embedded Communication Channel Operation This section describes the ECC operation. The ECC trans- mits one 8 byte message per frame over the link under software control. Flow control ensures that messages are not overwritten at the receive end. The ...
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Embedded Communication Channel Operation (Continued) Reset The transmit buffer ready ETXBR bit is set indicating that the transmit buffer ETXD7–ETXD0 can be written to and the Tx Buffer Freeze is clear (inactive). The transmit buffer send ETXSD bit is ...
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Embedded Communication Channel Operation 16.2 ECC OPERATION WITH ACTIVE AND STANDBY RECEIVERS The DS92UT16 has two independent receive sections, Port A and Port B. These each contain an ECC receive section and the ECC can be configured to receive ...
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Embedded Communication Channel Operation (Continued) Device 2 transmitter is connected to Device 1 receiver Port A. This is accomplished by clearing the RAESS bit of the RACTL register. ECC Receive on Port B: Device 1 communicating with Device 3 ...
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Embedded Communication Channel Operation FIGURE 18. ECC Signalling with Active and Standby Links 17.0 Microprocessor Interface Operation The DS92UT16 contains a flexible microprocessor port ca- pable of interfacing to either Intel or Motorola processors. In addition to an 8-bit ...
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Microprocessor Interface Operation No. 1 Address Setup Time before Chip Select Low 2 Chip Select Setup before Write Low 3 Write Pulse Width (Notes Data Setup before Write High (Notes Data Hold after ...
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Microprocessor Interface Operation No. 1 Address Setup Time before Chip Select Low 2 Chip Select Setup before Write Low 3 Read Pulse Width (Notes Read Low to Data Low Impedance 5 Read Low to Valid Data ...
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Microprocessor Interface Operation No. 1 Address Setup Time before Chip Select Low 2 Chip Select Setup before Data Strobe Low 3 Read/Write Setup before Data Strobe Low 4 Data Strobe Pulse Width (Notes Data Setup before ...
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Microprocessor Interface Operation No. 1 Address Setup Time before Chip Select Low 2 Chip Select Setup before Data Strobe Low 3 Read/Write Setup before Data Strobe Low 4 Data Strobe Pulse Width (Notes Data Strobe Low ...
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Register Description This section describes all the software accessible registers in the DS92UT16. A summary of all registers is shown in Table 20. Software Register Name Address Lock SLK0 0x00 SLK1 0x01 VID 0x02 GCS 0x03 LVC 0x04 PDUCFG ...
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Register Description Software Register Name Address Lock RAHECC2 0x2E RAHECC1 0x2F RAHECC0 0x30 RAHECT2 0x31 RAHECT1 0x32 RAHECT0 0x33 RABIPC2 0x34 RABIPC1 0x35 RABIPC0 0x36 RABIPT2 0x37 RABIPT1 0x38 RABIPT0 0x39 RAPA 0x3A RAPIE 0x3B RARA 0x3C RARIE 0x3D ...
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Register Description Software Register Name Address Lock ERBD4 0x69 ERBD3 0x6A ERBD2 0x6B ERBD1 0x6C ERBD0 0x6D RBHECC2 0x6E RBHECC1 0x6F RBHECC0 0x70 RBHECT2 0x71 RBHECT1 0x72 RBHECT0 0x73 RBBIPC2 0x74 RBBIPC1 0x75 RBBIPC0 0x76 RBBIPT2 0x77 RBBIPT1 0x78 ...
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Register Description Software Register Name Address Lock UCPL0 0xA4 Reserved 0xA5 UCSPL 0xA6 USPAL 0xA7 USPAM 0xA8 MTBQT30 0xA9 MTBQT29 0xAA MTBQT28 0xAB MTBQT27 0xAC MTBQT26 0xAD MTBQT25 0xAE MTBQT24 0xAF MTBQT23 0xB0 MTBQT22 0xB1 MTBQT21 0xB2 MTBQT20 0xB3 ...
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Register Description Software Register Name Address Lock MTBQF0 0xD3 MTBCF3 0xD4 MTBCF2 0xD5 MTBCF1 0xD6 MTBCF0 0xD7 QFL 0xD8 MTBQOV3 0xD9 MTBQOV2 0xDA MTBQOV1 0xDB MTBQOV0 0xDC Unused 0xDD to 0xDF D2ULBCC 0xE0 UAA 0xE1 UAIE 0xE2 Unused 0xE3 ...
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Register Description LOCK SEQUENCE 1. Write data 0xDE to SLK0. 2. Write data 0xAD to SLK1. The software lock is now ON and those registers protected by it cannot be written to. The order of the writes in each ...
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Register Description 18.4 LVDS CONTROL — 0x04 LVC 7 6 Reserved Reserved Type: Read/Write Software Lock: Yes Reset Value: 0x3B The LVDS control register configures the LVDS serializer/deserializers. • TXPWDN Transmit section LVDS power down. Set = Power Up ...
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Register Description 18.6 INTERRUPT SOURCE — 0x06 UAA ETXRXA Type: Read only/Clear on Read Software Lock: No Reset Value: 0x00 The Interrupt Source register reflects the source of pending interrupts. • UAA Set = Interrupt pending ...
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Register Description • ECCA ECC active on Port A bit. When set, this indicates to the ECC transmit section that the ETXBR bit (Section 18.10 ECC TRANSMIT BUFFER AND RECEIVE LVDS ALARMS — 0x0A ETXRXA) will be set only ...
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Register Description The ETXBR register bit indicates that the ECC transmit section has successfully transmitted the full ECC message consisting of the 8 data bytes contained in registers ETXD7–ETXD0 and a new message can be assembled and transmitted. This ...
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Register Description 7 6 ETXD2 0x12 ETXD2[7] ETXD2[6] ETXD1 0x13 ETXD1[7] ETXD1[6] ETXD0 0x14 ETXD0[7] ETXD0[6] Type: Read/Write Software Lock: No Reset Value: 0x00 The ETXD7, ETXD6, ETXD5, ETXD4, ETXD3, ETXD2, ETXD1 and ETXD0 registers contain the ECC message ...
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Register Description 7 6 ERRBIP1 0x17 EBIP1[7] EBIP1[6] ERRBIP0 0x18 EBIP0[7] EBIP0[6] Type: Read/Write Software Lock: Yes Reset Value: 0x00 The Error BIP Mask registers controls how errors are introduced into the BIP bytes when bit ERBIP of the ...
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Register Description 18.19 ATM LOOPBACK MPhy — 0x1B ALBMP 7 6 Reserved Reserved Type: Read/Write Software Lock: No Reset Value: 0x00 The ATM Loopback MPhy register defines the MPhy address attached to the ATM loopback cell. Setting the TXLVLB ...
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Register Description Type: Read only Software Lock: No Reset Value: 0x00 The Receive Port A Expected Link Label register defines the expected contents of the Link Trace Label byte received in TC6 on receive Port A. If the actual ...
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Register Description Type: Read/Write Software Lock: Yes Reset Value: 0x01 The Receive Port A Control register defines the operation of the Port A TCS DisAssembler section. • RAESS Receive Port A, Valid Received ESS bit select. Two ESS bits ...
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Register Description 18.28 RECEIVE PORT A HEC THRESHOLD — 0x31 to 0x33 RAHECT2 to RAHECT0 7 6 RAHECT2 RAHECT2[7] RAHECT2[6] 0x31 RAHECT1 RAHECT1[7] RAHECT1[6] 0x32 RAHECT0 RAHECT0[7] RAHECT0[6] 0x33 Type: Read/Write Software Lock: No Reset Value: 0xFF The RAHECT2, ...
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Register Description The Receive Port A Performance Alarms register contains information about the error performance of Port A. When set RAXHEC and RAXBIP will raise an interrupt if the corresponding interrupt enable bits are set. • RAXHEC Receive Port ...
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Register Description 18.35 RECEIVE PORT A UP2DOWN LOOPBACK CELL COUNT — 0x3E RAU2DLBC 7 6 RAU2DLBC[7] RAU2DLBC[6] RAU2DLBC[5] RAU2DLBC[4] RAU2DLBC[3] RAU2DLBC[2] RAU2DLBC[1] RAU2DLBC[0] Type: Read only/Clear on Read Software Lock: No Reset Value: 0x00 The Receive Port A Up2Down ...
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Register Description • PSI[3:0] When in lock this is the threshold that the descrambler confidence counter must reach to lose descrambler lock. When in lock the descrambler confidence counter increments on incorrect HEC predictions and decrements on good HEC ...
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Register Description Type: Read/Write Software Lock: No Reset Value: 0x00 The Receive Port B Expected Link Label register defines the expected contents of the Link Trace Label byte received in TC6 on receive Port B. If the actual received ...
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Register Description Type: Read/Write Software Lock: Yes Reset Value: 0x01 The Receive Port B Control register defines the operation of the Port B TCS DisAssembler section. • RBESS Receive Port B, Valid Received ESS bit select. Two ESS bits ...
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Register Description 18.47 RECEIVE PORT B HEC THRESHOLD — 0x71 to 0x73 RBHECT2 to RBHECT0 7 6 RBHECT2 RBHECT2[7] RBHECT2[6] 0x71 RBHECT1 RBHECT1[7] RBHECT1[6] 0x72 RBHECT0 RBHECT0[7] RBHECT0[6] 0x73 Type: Read/Write Software Lock: No Reset Value: 0xFF The RBHECT2, ...
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Register Description The Receive Port B Performance Alarms register contains information about the error performance of Port B. When set RBXHEC and RBXBIP will raise an interrupt if the corresponding interrupt enable bits are set. • RBXHEC Receive Port ...
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Register Description 18.54 RECEIVE PORT B UP2DOWN LOOPBACK CELL COUNT — 0x7E RBU2DLBC 7 6 RBU2DLBC[7] RBU2DLBC[6] RBU2DLBC[5] RBU2DLBC[4] RBU2DLBC[3] RBU2DLBC[2] RBU2DLBC[1] RBU2DLBC[0] Type: Read only/Clear on Read Software Lock: No Reset Value: 0x00 The Receive Port B Up2Down ...
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Register Description • PSI[3:0] When in lock this is the threshold that the descrambler confidence counter must reach to lose descrambler lock. When in lock the descrambler confidence counter increments on incorrect HEC predictions and decrements on good HEC ...
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Register Description • UCPL3–UCPL0 UCPL3[6] corresponds to port 31 and UCPL0[0] corresponds to port 0. When a bit is set then the port is connected and will be polled, when clear the port is not connected and will not ...
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Register Description 7 6 MTBQT1 0xC6 MTBQT1[7] MTBQT1[6] MTBQT0 0xC7 MTBQT0[7] MTBQT0[6] Type: Read/Write Software Lock: Yes Reset Value: 0x04 The MTB Queue Threshold registers define the maximum size, in PDU cells, of each of the 31 queues. If ...
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Register Description 7 6 MTBQF3 0xD0 Reserved MTBQF3[6] MTBQF2 0xD1 MTBQF2[7] MTBQF2[6] MTBQF1 0xD2 MTBQF1[7] MTBQF1[6] MTBQF0 0xD3 MTBQF0[7] MTBQF0[6] Type: Read/Write Software Lock: Yes Reset Value: 0x00 The MTBQF3, MTBQF2, MTBQF1 and MTBQF0 registers allow each of the ...
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Register Description 7 6 MTBQOV3 Reserved MTBQOV3[6] 0xD9 MTBQT29 MTBQOV2[7] MTBQOV2[6] 0xDA MTBQOV1 MTBQOV1[7] MTBQOV1[6] 0xDB MTBQOV0 MTBQOV0[7] MTBQOV0[6] 0xDC Type: Read only/Clear on Read Software Lock: No Reset Value: 0x00 The MTBQOV3, MTBQOV2, MTBQOV1 and MTBQOV0 registers indicate ...
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Register Description • FIBOV Set = FIB queue attempted to overflow (Equivalent functionality as the MTBQOV3–0 register bits). • MTBSOV MTB Soft Overflow Alarm bit. Set = One or more of the bits in the MTBQOV3–MTBQOV0 registers are set. ...
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Test Features (Continued) FIGURE 23. LOGICVISION TAP Instruction Register The TAP controller contains a device ID register which holds the device identification. Figure 24 shows the makeup of the device ID register and the device ID value for the ...
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Test Features (Continued) TABLE 95. (Continued) No. Pin Name 46 U_TXDATA_8 47 U_TXDATA_7 48 U_TXDATA_6 49 U_TXDATA_5 50 U_TXDATA_4 51 U_TXDATA_3 52 U_TXDATA_2 53 U_TXDATA_1 54 U_TXDATA_0 55 U_TXPARITY 56 U_TXCLAV_6 57 U_TXCLAV_5 58 U_TXCLAV_4 59 U_TXCLAV_3 60 U_TXCLAV_2 ...
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Package 196-ball LBGA. Dimensions 1.37 mm, 1.0 mm ball pitch. Ball Pin Name A2 AGND A12 AGND B11 AGND B13 AGND C4 AGND C7 AGND C13 AGND E7 AGND ...
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Package (Continued) TABLE 96. Pin Locations — BGA196 Package (Continued) Ball Pin Name N8 DGND K13 P10 A11 D10 ...
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Package (Continued) TABLE 96. Pin Locations — BGA196 Package (Continued) Ball Pin Name B8 PGND C8 PGND D8 PGND C9 PGNDA C11 PGNDA C12 PGNDA G9 PGNDA B5 PGNDB B6 PGNDB C5 PGNDB C6 PGNDB ...
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Package (Continued) TABLE 96. Pin Locations — BGA196 Package (Continued) Ball Pin Name K9 U_RxData [14] L9 U_RxData [15] J12 U_RxENB [0] L14 U_RxENB [1] M14 U_RxENB [2] L13 U_RxENB [3] G10 U_RxENB [4] J9 U_RxENB [5] K11 U_RxENB ...
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Package (Continued) TABLE 96. Pin Locations — BGA196 Package (Continued) Ball Pin Name L6 U_TxENB [7] J5 U_TxParity M8 U_TxSOC P8 U_UDBClk K12 U_UUBClk 21.0 References 1. The ATM Forum UTOPIA Level 2, Version 1.0 Specifica- tion, af-phy-0039.000, June ...
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... Absolute Maximum Ratings (Note 13) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage I CCIO Supply Voltage Core Internal (V CCINT CMOS/TTL Input and I/O Voltage CMOS/TTL Output Voltage LVDS DO/RIN Voltage ...
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Electrical Characteristics Bus LVDS DC Specifications Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14) LVDS Specifications are for LVDS Input and Output pins only. Control inputs and clocks are specified under Control Pin and Clocks ...
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Electrical Characteristics UTOPIA Bus Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14) Symbol Parameter t Input Data Valid before USETUP CLK t Input Data Valid after CLK UHOLD t Output Low-to-High ULH Transition ...
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Electrical Characteristics LVDS Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 14) Symbol Parameter t Deserializer PLL Lock DSR1 Time from PWRDN (with SYNCPAT) t Deserializer PLL Lock DRS2 Time from SYNCPAT t Deserializer ...
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Electrical Characteristics www.national.com (Continued) FIGURE 25. LVDS Rise and Fall times FIGURE 26. CMOS Rise and Fall times 20031630 FIGURE 27. REFCLK Transition time FIGURE 28. Deserializer lock time t DSR1 80 20031628 20031629 20031634 ...
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Electrical Characteristics FIGURE 31. UTOPIA Setup and Hold Time Definition (Continued) FIGURE 29. Deserializer lock time t DSR2 FIGURE 30. Deserializer Noise Margin FIGURE 32. UTOPIA TRI-STATE Timing 81 20031635 20031636 20031638 20031639 www.national.com ...
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Electrical Characteristics Signal Name DIR A → P U_UDBClk, U_UUBClk A → P U_TxData[15:0], U_TxPrty, U_TxSOC, U_TxEnb[7:0], U_TxAddr[4:0] A ← P U_TxClav [7:0] Signal Name DIR A → P U_UDBClk, U_UUBClk A → P U_RxEnb[7:0], U_RxAddr[4:0] A ← P ...
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Appendix A: Layout and Connection Guidelines FIGURE 33. Block Diagram Is a Top View of 196 LBGA Ball Assignment. 83 20031624 www.national.com ...
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Appendix A: Layout and Connection Guidelines 25.1 POWER CONNECTIONS 25.1.1 Digital Supplies (DV and DGND) DD The digital supply pins provide power to the digital section of the device. Since the digital supplies are subject to switching noise, the ...
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Appendix A: Layout and Connection Guidelines FIGURE 34. Recommended bypassing and filtering for the Analog and PLL power supplies on the DS92UT16 FIGURE 35. Diagram shows routing high-speed LVDS lines on one layer to a connector header. (Continued) Utopia-LVDS ...
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... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...