LAN9303MI-AKZE Standard Microsystems (SMSC), LAN9303MI-AKZE Datasheet - Page 264

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LAN9303MI-AKZE

Manufacturer Part Number
LAN9303MI-AKZE
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet

Specifications of LAN9303MI-AKZE

Lead Free Status / Rohs Status
Compliant
Revision 1.4 (07-07-10)
13.4.2.24
31:18
17:16
BITS
15:0
RESERVED
Backoff Reset RX/TX
Half duplex-only. Determines when the truncated binary exponential backoff
attempts counter is reset.
00 = Reset on successful transmission (IEEE standard)
01 = Reset on successful reception
1X = Reset on either successful transmission or reception
Pause Time Value
The value that is inserted into the transmitted pause packet when the switch
wants to “XOFF” its link partner.
Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x)
This read/write register configures the flow control settings of the port.
Register #:
Port0: 0441h
Port1: 0841h
Port2: 0C41h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Dual MII/RMII/Turbo MII
DATASHEET
264
Size:
32 bits
SMSC LAN9303M/LAN9303Mi
TYPE
R/W
R/W
RO
DEFAULT
FFFFh
00b
Datasheet
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