MT48LC4M16A2P-75 L:GTR Micron Technology Inc, MT48LC4M16A2P-75 L:GTR Datasheet - Page 54
MT48LC4M16A2P-75 L:GTR
Manufacturer Part Number
MT48LC4M16A2P-75 L:GTR
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC4M16A2P-75_LGTR.pdf
(72 pages)
Specifications of MT48LC4M16A2P-75 L:GTR
Organization
4Mx16
Density
64Mb
Address Bus
14b
Access Time (max)
6/5.4ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
140mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
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Figure 37:
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. N 12/08 EN
DQML, DQMH
A0–A9, A11
COMMAND
DQM /
BA0, BA1
CLK
CKE
A10
DQ
t CMS
t CKS
t AS
t AS
t AS
COLUMN m
READ
T0
BANK
Clock Suspend Mode
t CMH
t CKH
t AH
t AH
t AH
2
Notes:
t CMS
t CK
T1
NOP
t CMH
1. For this example, BL = 2, CL = 3, and auto precharge is disabled.
2. x16: A8, A9 and A11 = “Don’t Care”
x8: A9 and A11 = “Don’t Care”
x4: A11 = “Don’t Care”
t CL
t CKS t CKH
T2
NOP
t LZ
t CH
AC
T3
D
OUT
m
T4
NOP
54
t OH
t AC
D
T5
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
m + 1
t HZ
T6
NOP
64Mb: x4, x8, x16 SDRAM
COLUMN e 2
t DS
BANK
WRITE
D
T7
IN
e
t DH
©2000 Micron Technology, Inc. All rights reserved.
Timing Diagrams
T8
D
DON’T CARE
UNDEFINED
IN
T9
NOP
e + 1
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