SL72P8M64M8M-A05AYU STEC, SL72P8M64M8M-A05AYU Datasheet - Page 18

• Manufacturer Part Number: SL72P8M64M8M-A05AYU
• Manufacturer: STEC

Specifications of SL72P8M64M8M-A05AYU

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Access Time (max): 600ps
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.17A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / Rohs Status: Compliant

SL72P8M64M8M-A05AY(W)U
PLL CLOCK DRIVER ELECTRICAL CHARACTERISTICS
Recommended Operating Temperature Range; AVDDQ = VDDQ = +1.8V ±0.1V unless otherwise stated.
PLL CLOCK DRIVER TIMING REQUIREMENTS
Recommended Operating Temperature Range; AVDDQ = VDDQ = +1.8V ±0.01V unless otherwise stated.
PLL CLOCK DRIVER SWITCHING CHARACTERISTICS
Recommended Operating Temperature Range; AVDDQ = VDDQ = +1.8V ±0.1V unless otherwise stated.
Symbol Parameters
VIH
VIL
VIN
VIH
VIL
VIX
VID(DC) Input Differential Voltage for CK, /CK
VID(AC) Input Differential Voltage for CK, /CK
I
I
IODL
IDD1.8
IDDLD
VOH
VOL
CI
Symbol
freqOP
freqAPP
dTIN
tSTAB
Symbol
tEN
tDIS
tJIT(PER)
tJIT(HPER)
SLr1(i)
SLr1(o)
tJIT(cc+)
tJIT(cc-)
t(phase)DYN Dynamic Phase Offset
tSPO
tSKEW
I
I
DC High-Level Input Voltage for /RESET LVCMOS
DC Low-Level Input Voltage for /RESET LVCMOS
Input Voltage Limits for CK, /CK,
/RESET
DC High-Level Input Voltage for CK, /CK Differential Input
DC Low-Level Input Voltage for CK, /CK Differential Input
Input Differential-Pair Cross Voltage
Input Current for CK, /CK
Input Current for /RESET
Output Disabled Low Current
Dynamic Operating Supply Current
Static Supply Current
High-level Output Voltage
Low-level Output Voltage
Input Capacitance (PCB not included)
Parameters
Max Clock Frequency
Application Frequency Range
Input Clock Duty Cycle
CLK Stabilization
Parameters
Output Enable Time
Output Disable Time
Period Jitter
Half-period Jitter
Input Slew Rate
Output Clock Slew Rate
Cycle-to-Cycle Period Jitter
Static Phase Offset
(Does not include jitter)
Output to Output Skew
SSC Modulation Frequency
SSC Clock Input Frequency Deviation
PLL Loop Bandwidth
(-3 dB MHz from Unity Gain)
Conditions
Differential Input
Differential Input
Differential Input
VI = VDDQ or GND
/RESET = L, VODL = 100mV
CL = 0pf @ 270MHz
CL = 0pf
IOH = -100 µA
IOH = -9 mA
IOL=100 µA
IOL=9 mA
VI = GND or VDDQ
VI = VDDQ or GND
1.8V+0.1V @ 25°C
1.8V+0.1V @ 25°C
Conditions
Conditions
/RESET to any Output
/RESET to any Output
Input Clock
Output Enable (/RESET)
Document Part Number 61000-03657-105 November 2007 Page 18
Min
125
160
40
0.50 x VDDQ - 150 0.50 x VDDQ + 150
VDDQ - 200
0.65 x VDD
0.65 x VDD
1100
-300
Min
300
600
100
2
Min
-30
-40
0.5
-10
-50
30
Max
1
1
0
0
0
2
500
400
60
10
Typ
2.5
0
VDDQ + 300
VDDQ + 400
VDDQ + 400
0.35 x VDD
0.35 x VDD
240-PIN RDIMM
Units
MHz
MHz
µs
%
Max
±250
±10
150
500
100
600
3
Max
-0.5
-30
30
40
30
10
50
35
33
8
8
4
Units
Units
MHz
mV
mV
mV
mV
mV
mV
mV
mV
mA
mV
mV
mV
mV
v/ns
v/ns
v/ns
kHz
µA
µA
µA
µA
pF
ns
ns
ps
ps
ps
ps
ps
ps
ps
%