K4H281638B-TCB0000 Samsung Semiconductor, K4H281638B-TCB0000 Datasheet - Page 42

• Manufacturer Part Number: K4H281638B-TCB0000
• Manufacturer: Samsung Semiconductor

Specifications of K4H281638B-TCB0000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

128Mb DDR SDRAM
Notes 1. Includes
Typical case: VDD = 2.5V, T = 25’C
Worst case : VDD = 2.7V, T = 10’C
7.2 DDR SDRAM SPEC Items and Test Conditions
Conditions
Operating current - One bank Active-Precharge;
tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating current - One bank operation ; One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
Percharge power-down standby current; All banks idle; power - down mode;
CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
Precharge Quiet standby current; CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Active power - down standby current ; one bank active; power-down mode;
CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
Operating current - burst read; Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =
133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A
Operating current - burst write; Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
Self refresh current; CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
Orerating current - Four bank operation ; Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
Vin = Vref for DQ ,DQS and DM
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,
3. V
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in
5. The value of V
2.V
bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on V
TO V
V
simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ.
REF
ID
TT
is the magnitude of the difference between the input level on CK and the input level on CK.
is not applied directly to the device. V
, and must track variations in the DC level of V
REF
, both of which may result in V
25mV margin for DC offset on V
IX
is expected to equal 0.5*V
REF
TT
noise. V
REF
DDQ
is a system supply for signal termination resistors, is expected to be set equal to
, and a combined total of
of the transmitting device and must track variations in the dc level of the same.
REF
REF
- 42 -
should be de-coupled with an inductance of
50mV margin for all AC noise and DC offset on V
REV. 1.31 Nov. 3. 2001
REF
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
and internal DRAM noise coupled
Symbol
3nH.
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Typical
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Worst
REF
,