CY7C4261-10JI Cypress Semiconductor Corp, CY7C4261-10JI Datasheet
CY7C4261-10JI
Specifications of CY7C4261-10JI
Related parts for CY7C4261-10JI
CY7C4261-10JI Summary of contents
Page 1
... WCLK cycle. The output port is controlled in a similar manner by a free running read clock (RCLK) and two read enable pins (REN1, REN2). In addition, the CY7C4261/71 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... CONTROL WRITE POINTER RESET RS LOGIC Document #: 38-06015 Rev 0–8 INPUT REGISTER WEN2/ LD RAM ARRAY 16K x 9 32K x 9 THREE-STATE OUTPUT REGISTER OE Q 0–8 RCLK CY7C4261, CY7C4261 FLAG PROGRAM REGISTER EF PAE FLAG LOGIC PAF FF READ POINTER READ CONTROL REN1 REN2 Page [+] Feedback ...
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... HIGH, the FIFO’s outputs are in High Z (high impedance) state. Document #: 38-06015 Rev. *D Figure 2. Pin Diagram - 32-Pin TQFP (Top View WEN1 D 0 WCLK PAF LD WEN2/ PAE V CC GND REN1 7 Q RCLK REN2 Description CY7C4261, CY7C4261 WEN1 2 23 WCLK 3 WEN2/LD 22 CY7C4261 CY7C4271 ...
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... Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Architecture The CY7C4261/71 consists of an array of 16K to 32K words of nine bits each (implemented by a dual port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF) ...
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... FF). The partial status flags (PAE and PAF) can be detected from any one device. Selection a 18-bit word width by using two CY7C4261/71s. Any word width can be attained by adding additional CY7C4261/71s. When the CY7C4261/ Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (see Figure 4 on page 6) ...
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... WRITE ENABLE 2/LOAD (WEN2/LD) PROGRAMMABLE(PAF) FULL FLAG (FF FULL FLAG (FF Read Enable 2 (REN2) Document #: 38-06015 Rev. *D RESET (RS) RESET (RS) 9 CY7C4261/71 CY7C4261/ Read Enable 2 (REN2) CY7C4261, CY7C4261 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF DATA OUT ( Page [+] Feedback ...
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... OE > V −10 − < V < Com’l 35 Ind/Mil 40 Com’l 10 Ind/Mil 15 Test Conditions ° MHz 5.0V CC CY7C4261, CY7C4261 Ambient Temperature V CC ° ° 5V ± 10 +70 C ° ° −40 5V ± 10 +85 C ° ° −55 5V ± 10 +125 C Max Min Max Min Max 2.4 2.4 ...
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... Figure 5. AC Test Loads and Waveforms R1 1.1KΩ 3.0V GND R2 680Ω 1.91V 7C4261/71-10 7C4261/71-15 Min Max Min 100 4 [13 [13 CY7C4261, CY7C4261 [10, 11] ALL INPUT PULSES 90% 90% 10% 10% ≤3 ns ≤ 7C4261/71-25 7C4261/71- 35 Max Min Max Min Max 66 ...
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... NO OPERATION t REF t A VALID DATA t OE [15] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4261, CY7C4261 NO OPERATION NO OPERATION t WFF t REF t OHZ Page [+] Feedback ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06015 Rev. *D [16] Figure 8. Reset Timing RSS t t RSS t t RSS t RSF t RSF t RSF [19] t FRL t SKEW1 t REF [20 OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4261, CY7C4261 RSR RSR RSR [17 (maximum) = either 2 FRL CLK SKEW1 Page CLK [+] Feedback ...
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... Document #: 38-06015 Rev. *D Figure 10. Empty Flag Timing [19 REF REF t A Figure 11. Full Flag Timing t DS DATA WRITE t WFF t ENH t A DATA READ CY7C4261, CY7C4261 DATA WRITE 2 t ENH ENS t ENH ENS [19] t FRL t t REF SKEW1 DATA READ NO WRITE [14] DATA WRITE t SKEW1 t WFF t ...
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... If a write is performed on this rising edge of the write clock, there are Full − (m−1) words of the FIFO when PAF goes LOW. 25. PAF offset = m. 26. 16,384 − m words for CY7C4261, 32,768 − m words for CY7C4271. 27 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of ...
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... Figure 14. Write Programmable Registers t CLKL t ENH t DH PAE OFFSET PAF OFFSET LSB MSB Figure 15. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET LSB CY7C4261, CY7C4261 PAF OFFSET LSB MSB PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB Page [+] Feedback ...
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... AMBIENT TEMPERATURE (°C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 −55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE (°C) CY7C4261, CY7C4261 vs. AMBIENT 5.0V CC 5.00 65.00 125.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1. 25° ...
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... Ordering Information 16Kx9 Deep Sync FIFO Speed (ns) Ordering Code Package Diagram CY7C4261-10AC CY7C4261-10JC 10 CY7C4261-10AI CY7C4261-10JI CY7C4261-10JXI CY7C4261-15AC CY7C4261-15JC 15 CY7C4261-15JXC CY7C4261-15AI CY7C4261-15JI CY7C4261-25AC CY7C4261-25JC 25 CY7C4261-25AI CY7C4261-25JI CY7C4261-35AC CY7C4261-35JC 35 CY7C4261-35AI CY7C4261-35JI 32Kx9 Deep Sync FIFO Speed (ns) Ordering Code Package Diagram 10 CY7C4271-10AC CY7C4271-10JC CY7C4271-10AI ...
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... HFH t 9, 10, 11 FFH t 9, 10, 11 REF Document #: 38-06015 Rev. *D Table 5. Switching Characteristics (continued) Subgroups Parameters t RFF t WEF t WFF t WHF t RHF t RAE t RPE t WAF t WPF t XOL t XOH Subgroups CY7C4261, CY7C4261 Subgroups 10, 11 Page [+] Feedback ...
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... Package Diagrams Figure 17. 32-Pin Thin Plastic Quad Flatpack (7 × 7 × 1.0 mm) Document #: 38-06015 Rev. *D Figure 18. 32-Pin Plastic Leaded Chip Carrier CY7C4261, CY7C4261 51-85063 *B 51-85002 *B Page [+] Feedback ...
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... Package Diagrams (continued) Figure 19. 32-Pin Rectangular Leadless Chip Carrier Document #: 38-06015 Rev. *D CY7C4261, CY7C4261 MIL-STD-1835 C-12 51-80068-** Page [+] Feedback ...
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... Document History Page Document Title: CY7C4261/CY7C4271, 16K/32K x 9 Deep Sync FIFOs Document Number: 38-06015 Orig. of Submission REV. ECN Change ** 106476 SZV *A 122267 RBI *B 127853 FSG *C 393437 ESH *D 2556036 VKN/AESA Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...